Flow-Through SRAM Specification Sheet

ManualsBrandsCypress ManualsComputer HardwareCY7C1473V33

72-Mbit (2M x 36/4M x 18/1M x 72)

Flow-Through SRAM with NoBL™ Architecture

CY7C1471V33

CY7C1473V33

CY7C1475V33

Cypress Semiconductor Corporation • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600

Document #: 38-05288 Rev. *J Revised July 04, 2007

Features

• No Bus Latency™ (NoBL™) architecture eliminates dead

cycles between write and read cycles

• Supports up to 133 MHz bus operations with zero wait states

• Data is transferred on every clock

• Pin compatible and functionally equivalent to ZBT™ devices

• Internally self timed output buffer control to eliminate the

need to use OE

• Registered inputs for flow through operation

• Byte Write capability

• 3.3V/2.5V IO supply (V

DDQ

)

• Fast clock-to-output times

— 6.5 ns (for 133-MHz device)

• Clock Enable (CEN) pin to enable clock and suspend

operation

• Synchronous self timed writes

• Asynchronous Output Enable (OE)

• CY7C1471V33, CY7C1473V33 available in

JEDEC-standard Pb-free 100-Pin TQFP, Pb-free and

non-Pb-free 165-Ball FBGA package. CY7C1475V33

available in Pb-free and non-Pb-free 209-Ball FBGA

package

• Three Chip Enables (CE

, CE

) for simple depth

expansion

• Automatic power down feature available using ZZ mode or

CE deselect

• IEEE 1149.1 JTAG Boundary Scan compatible

• Burst Capability — linear or interleaved burst order

• Low standby power

Functional Description

[1]

The CY7C1471V33, CY7C1473V33 and CY7C1475V33 are

3.3V, 2M x 36/4M x 18/1M x 72 synchronous flow through burst

SRAMs designed specifically to support unlimited true

back-to-back read or write operations without the insertion of

wait states. The CY7C1471V33, CY7C1473V33 and

CY7C1475V33 are equipped with the advanced No Bus

Latency (NoBL) logic required to enable consecutive read or

write operations with data being transferred on every clock

cycle. This feature dramatically improves the throughput of

data through the SRAM, especially in systems that require

frequent write-read transitions.

All synchronous inputs pass through input registers controlled

by the rising edge of the clock. The clock input is qualified by

the Clock Enable (CEN

) signal, which when deasserted

suspends operation and extends the previous clock

cycle.Maximum access delay from the clock rise is 6.5 ns

(133-MHz device).

Write operations are controlled by two or four Byte Write Select

(BW

) and a Write Enable (WE) input. All writes are conducted

with on-chip synchronous self timed write circuitry.

Three synchronous Chip Enables (CE

, CE

) and an

asynchronous Output Enable (OE

) provide for easy bank

selection and output tri-state control. To avoid bus contention,

the output drivers are synchronously tri-stated during the data

portion of a write sequence.

Selection Guide

133 MHz 117 MHz Unit

Maximum Access Time 6.5 8.5 ns

Maximum Operating Current 305 275 mA

Maximum CMOS Standby Current 120 120 mA

Note

1. For best practice recommendations, refer to the Cypress application note AN1064, SRAM System Guidelines.

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Summary of content (32 pages)

PAGE 1
CY7C1471V33 CY7C1473V33 CY7C1475V33 72-Mbit (2M x 36/4M x 18/1M x 72) Flow-Through SRAM with NoBL™ Architecture Functional Description [1] Features • No Bus Latency™ (NoBL™) architecture eliminates dead cycles between write and read cycles • Supports up to 133 MHz bus operations with zero wait states • Data is transferred on every clock • Pin compatible and functionally equivalent to ZBT™ devices • Internally self timed output buffer control to eliminate the need to use OE • Registered inputs for flow thr
PAGE 2
CY7C1471V33 CY7C1473V33 CY7C1475V33 Logic Block Diagram – CY7C1471V33 (2M x 36) ADDRESS REGISTER A0, A1, A A1 D1 A0 D0 MODE CLK CEN CE C ADV/LD C BURST LOGIC Q1 A1' A0' Q0 WRITE ADDRESS REGISTER ADV/LD BW A WRITE DRIVERS WRITE REGISTRY AND DATA COHERENCY CONTROL LOGIC BW B BW C MEMORY ARRAY S E N S E A M P S BW D WE INPUT REGISTER OE CE1 CE2 CE3 D A T A S T E E R I N G O U T P U T B U F F E R S DQs DQP A DQP B DQP C DQP D E E READ LOGIC SLEEP CONTROL ZZ Logic Block Diagram – CY7C14
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CY7C1471V33 CY7C1473V33 CY7C1475V33 Logic Block Diagram – CY7C1475V33 (1M x 72) ADDRESS REGISTER 0 A0, A1, A MODE CLK ADV/LD C C CEN A1 A1' D1 Q1 A0 A0' D0 BURST Q0 LOGIC WRITE ADDRESS REGISTER 2 WRITE ADDRESS REGISTER 1 ADV/LD BW a BW b BW c BW d BW e BW f BW g BW h WRITE REGISTRY AND DATA COHERENCY CONTROL LOGIC WRITE DRIVERS MEMORY ARRAY S E N S E A M P S O U T P U T R E G I S T E R S D A T A S T E E R I N G E O U T P U T B U F F E R S E DQ s DQ Pa DQ Pb DQ Pc DQ Pd DQ Pe DQ Pf DQ Pg D
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CY7C1471V33 CY7C1473V33 CY7C1475V33 Pin Configurations A 40 41 42 43 44 45 46 47 48 49 50 A A A A A A A A A 37 A0 VSS 36 A1 VDD 35 A 39 34 A NC/144M 33 A 38 32 NC/288M 31 Document #: 38-05288 Rev.
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CY7C1471V33 CY7C1473V33 CY7C1475V33 Pin Configurations (continued) A 40 41 42 43 44 45 46 47 48 49 50 A A A A A A A A A 37 A0 VSS 36 A1 VDD 35 A 39 34 A NC/144M 33 A 38 32 NC/288M 31 Document #: 38-05288 Rev.
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CY7C1471V33 CY7C1473V33 CY7C1475V33 Pin Configurations (continued) 165-Ball FBGA (15 x 17 x 1.
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CY7C1471V33 CY7C1473V33 CY7C1475V33 Pin Configurations (continued) 209-Ball FBGA (14 x 22 x 1.
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CY7C1471V33 CY7C1473V33 CY7C1475V33 Pin Definitions Name IO Description A0, A1, A InputSynchronous Address Inputs used to select one of the address locations. Sampled at the rising edge of the CLK. A[1:0] are fed to the two-bit burst counter. BWA, BWB, BWC, BWD, BWE, BWF, BWG, BWH InputSynchronous Byte Write Inputs, Active LOW. Qualified with WE to conduct writes to the SRAM. Sampled on the rising edge of CLK. WE InputSynchronous Write Enable Input, Active LOW.
PAGE 9
CY7C1471V33 CY7C1473V33 CY7C1475V33 Pin Definitions (continued) Name TDO IO JTAG serial output Synchronous Description Serial data-out to the JTAG circuit. Delivers data on the negative edge of TCK. If the JTAG feature is not used, this pin must be left unconnected. This pin is not available on TQFP packages. TDI JTAG serial input Serial data-In to the JTAG circuit. Sampled on the rising edge of TCK.
PAGE 10
CY7C1471V33 CY7C1473V33 CY7C1475V33 The data written during the write operation is controlled by BWX signals. The CY7C1471V33, CY7C1473V33, and CY7C1475V33 provides Byte Write capability that is described in the “Truth Table for Read/Write” on page 12. The input WE with the selected BWX input selectively writes to only the desired bytes. Bytes not selected during a Byte Write operation remain unaltered. A synchronous self timed write mechanism has been provided to simplify the write operations.
PAGE 11
CY7C1471V33 CY7C1473V33 CY7C1475V33 Truth Table The truth table for CY7C1471V33, CY7C1473V33, CY7C1475V33 follows.
PAGE 12
CY7C1471V33 CY7C1473V33 CY7C1475V33 Truth Table for Read/Write The read-write truth table for CY7C1471V33 follows.[2, 3, 9] Function WE BWA BWB BWC BWD Read H X X X X Write No bytes written L H H H H Write Byte A – (DQA and DQPA) L L H H H Write Byte B – (DQB and DQPB) L H L H H Write Byte C – (DQC and DQPC) L H H L H Write Byte D – (DQD and DQPD) L H H H L Write All Bytes L L L L L Truth Table for Read/Write The read-write truth table for CY7C1473V33 follows.
PAGE 13
CY7C1471V33 CY7C1473V33 CY7C1475V33 IEEE 1149.1 Serial Boundary Scan (JTAG) Test Access Port (TAP) The CY7C1471V33, CY7C1473V33, and CY7C1475V33 incorporate a serial boundary scan test access port (TAP). This port operates in accordance with IEEE Standard 1149.1-1990 but does not have the set of functions required for full 1149.1 compliance. These functions from the IEEE specification are excluded because their inclusion places an added delay in the critical speed path of the SRAM.
PAGE 14
CY7C1471V33 CY7C1473V33 CY7C1475V33 TAP Registers Registers are connected between the TDI and TDO balls and enable data to be scanned into and out of the SRAM test circuitry. Only one register can be selected at a time through the instruction register. Data is serially loaded into the TDI ball on the rising edge of TCK. Data is output on the TDO ball on the falling edge of TCK. nstruction Register Three-bit instructions can be serially loaded into the instruction register.
PAGE 15
CY7C1471V33 CY7C1473V33 CY7C1475V33 Note that since the PRELOAD part of the command is not implemented, putting the TAP to the Update-DR state while performing a SAMPLE/PRELOAD instruction has the same effect as the Pause-DR command. signal while in transition (metastable state). This does not harm the device, but there is no guarantee as to the value that is captured. Repeatable results may not be possible.
PAGE 16
CY7C1471V33 CY7C1473V33 CY7C1475V33 TAP AC Switching Characteristics Over the Operating Range[10, 11] Parameter Description Min Max Unit Clock tTCYC TCK Clock Cycle Time tTF TCK Clock Frequency tTH TCK Clock HIGH time 20 ns tTL TCK Clock LOW time 20 ns 50 ns 20 MHz Output Times tTDOV TCK Clock LOW to TDO Valid tTDOX TCK Clock LOW to TDO Invalid 5 ns 0 ns 5 ns Setup Times tTMSS TMS Setup to TCK Clock Rise tTDIS TDI Setup to TCK Clock Rise 5 ns tCS Capture Setup to TCK Ris
PAGE 17
CY7C1471V33 CY7C1473V33 CY7C1475V33 3.3V TAP AC Test Conditions 2.5V TAP AC Test Conditions Input pulse levels ................................................ VSS to 3.3V Input pulse levels................................................. VSS to 2.5V Input rise and fall times ................................................... 1 ns Input rise and fall time .....................................................1 ns Input timing reference levels ...........................................1.
PAGE 18
CY7C1471V33 CY7C1473V33 CY7C1475V33 Identification Register Definitions CY7C1471V33 (2Mx36) CY7C1473V33 (4Mx18) CY7C1475V33 (1Mx72) 000 000 000 01011 01011 01011 Architecture/Memory Type(23:18) 001001 001001 001001 Defines memory type and architecture Bus Width/Density(17:12) 100100 010100 110100 Defines width and density 00000110100 00000110100 00000110100 1 1 1 Instruction Field Revision Number (31:29) Device Depth (28:24) [13] Cypress JEDEC ID Code (11:1) ID Register Presence I
PAGE 19
CY7C1471V33 CY7C1473V33 CY7C1475V33 Boundary Scan Exit Order (2M x 36) Bit # 165-Ball ID Bit # 165-Ball ID Bit # 165-Ball ID Bit # 165-Ball ID 1 C1 21 R3 41 J11 61 B7 2 D1 22 P2 42 K10 62 B6 3 E1 23 R4 43 J10 63 A6 4 D2 24 P6 44 H11 64 B5 5 E2 25 R6 45 G11 65 A5 6 F1 26 R8 46 F11 66 A4 7 G1 27 P3 47 E11 67 B4 8 F2 28 P4 48 D10 68 B3 9 G2 29 P8 49 D11 69 A3 10 J1 30 P9 50 C11 70 A2 11 K1 31 P10 51 G10 71 B2 12 L1
PAGE 20
CY7C1471V33 CY7C1473V33 CY7C1475V33 Boundary Scan Exit Order (1M x 72) Bit # 209-Ball ID Bit # 209-Ball ID Bit # 209-Ball ID Bit # 209-Ball ID 1 A1 29 T1 57 U10 85 B11 2 A2 30 T2 58 T11 86 B10 3 B1 31 U1 59 T10 87 A11 4 B2 32 U2 60 R11 88 A10 5 C1 33 V1 61 R10 89 A7 6 C2 34 V2 62 P11 90 A5 7 D1 35 W1 63 P10 91 A9 8 D2 36 W2 64 N11 92 U8 9 E1 37 T6 65 N10 93 A6 10 E2 38 V3 66 M11 94 D6 11 F1 39 V4 67 M10 95 K6 12
PAGE 21
CY7C1471V33 CY7C1473V33 CY7C1475V33 Maximum Ratings DC Input Voltage ................................... –0.5V to VDD + 0.5V Exceeding maximum ratings may impair the useful life of the device. These user guidelines are not tested. Storage Temperature ................................. –65°C to +150°C Ambient Temperature with Power Applied............................................. –55°C to +125°C Current into Outputs (LOW)......................................... 20 mA Static Discharge Voltage..........
PAGE 22
CY7C1471V33 CY7C1473V33 CY7C1475V33 Capacitance Tested initially and after any design or process change that may affect these parameters. Parameter Description Test Conditions 100 TQFP Package 165 FBGA Package 209 BGA Package Unit TA = 25°C, f = 1 MHz, VDD = 3.3V VDDQ = 2.
PAGE 23
CY7C1471V33 CY7C1473V33 CY7C1475V33 Switching Characteristics Over the Operating Range. Unless otherwise noted in the following table, timing reference level is 1.5V when VDDQ = 3.3V and is 1.25V when VDDQ = 2.5V. Test conditions shown in (a) of “AC Test Loads and Waveforms” on page 22 unless otherwise noted. Description Parameter tPOWER [16] 133 MHz Min Max 117 MHz Min Max Unit 1 1 ms Clock tCYC Clock Cycle Time 7.5 10 ns tCH Clock HIGH 2.5 3.0 ns tCL Clock LOW 2.5 3.
PAGE 24
CY7C1471V33 CY7C1473V33 CY7C1475V33 Switching Waveforms Figure 1 shows read-write timing waveform.[20, 21, 22] Figure 1.
PAGE 25
CY7C1471V33 CY7C1473V33 CY7C1475V33 Switching Waveforms (continued) [20, 21, 23] Figure 2 shows NOP, STALL and DESELECT Cycles waveform. Figure 2. NOP, STALL and DESELECT Cycles 1 2 A1 A2 3 4 5 A3 A4 6 7 8 9 10 CLK CEN CE ADV/LD WE BW [A:D] ADDRESS A5 t CHZ D(A1) DQ Q(A2) Q(A3) D(A4) Q(A5) t DOH COMMAND WRITE D(A1) READ Q(A2) STALL READ Q(A3) WRITE D(A4) DON’T CARE STALL NOP READ Q(A5) DESELECT CONTINUE DESELECT UNDEFINED Note 23.
PAGE 26
CY7C1471V33 CY7C1473V33 CY7C1475V33 Switching Waveforms (continued) Figure 3 shows ZZ Mode timing waveform. [24, 25] Figure 3. ZZ Mode Timing CLK t ZZ I t ZZREC ZZ t ZZI SUPPLY I DDZZ t RZZI ALL INPUTS (except ZZ) Outputs (Q) DESELECT or READ Only High-Z DON’T CARE Notes 24. Device must be deselected when entering ZZ mode. See “Truth Table” on page 11 for all possible signal conditions to deselect the device. 25. DQs are in high-Z when exiting ZZ sleep mode. Document #: 38-05288 Rev.
PAGE 27
CY7C1471V33 CY7C1473V33 CY7C1475V33 Ordering Information Not all of the speed, package and temperature ranges are available. Please contact your local sales representative or visit www.cypress.com for actual products offered. Speed Package Operating Part and Package Type (MHz) Ordering Code Diagram Range 133 CY7C1471V33-133AXC 51-85050 100-Pin Thin Quad Flat Pack (14 x 20 x 1.4 mm) Pb-Free Commercial CY7C1473V33-133AXC CY7C1471V33-133BZC 51-85165 165-Ball Fine-Pitch Ball Grid Array (15 x 17 x 1.
PAGE 28
CY7C1471V33 CY7C1473V33 CY7C1475V33 Package Diagrams Figure 4. 100-Pin Thin Plastic Quad Flatpack (14 x 20 x 1.4 mm), 51-85050 16.00±0.20 1.40±0.05 14.00±0.10 100 81 80 1 20.00±0.10 22.00±0.20 0.30±0.08 0.65 TYP. 30 12°±1° (8X) SEE DETAIL A 51 31 50 0.20 MAX. R 0.08 MIN. 0.20 MAX. 0.10 1.60 MAX. 0° MIN. SEATING PLANE STAND-OFF 0.05 MIN. 0.15 MAX. 0.25 NOTE: 1. JEDEC STD REF MS-026 GAUGE PLANE 0°-7° R 0.08 MIN. 0.20 MAX. 2.
PAGE 29
CY7C1471V33 CY7C1473V33 CY7C1475V33 Package Diagrams (continued) Figure 5. 165-Ball FBGA (15 x 17 x 1.4 mm), 51-85165 PIN 1 CORNER BOTTOM VIEW TOP VIEW Ø0.05 M C PIN 1 CORNER Ø0.25 M C A B Ø0.45±0.05(165X) 1 2 3 4 5 6 7 8 9 10 11 11 10 9 8 7 6 5 4 3 2 1 A B B C C 1.00 A D D F F G G H J 14.00 E 17.00±0.10 E H J K L L 7.00 K M M N N P P R R A 1.00 5.00 0.35 0.15 C +0.05 -0.10 0.53±0.05 0.25 C 10.00 B 15.00±0.10 0.
PAGE 30
CY7C1471V33 CY7C1473V33 CY7C1475V33 Package Diagrams (continued) Figure 6. 209-Ball FBGA (14 x 22 x 1.76 mm), 51-85167 51-85167-** NoBL and No Bus Latency are trademarks of Cypress Semiconductor Corporation. ZBT is a trademark of Integrated Device Technology, Inc. All product and company names mentioned in this document are the trademarks of their respective holders. Document #: 38-05288 Rev. *J Page 30 of 32 © Cypress Semiconductor Corporation, 2002-2007.
PAGE 31
CY7C1471V33 CY7C1473V33 CY7C1475V33 Document History Page Document Title: CY7C1471V33/CY7C1473V33/CY7C1475V33, 72-Mbit (2M x 36/4M x 18/1M x 72) Flow-Through SRAM with NoBL™ Architecture Document Number: 38-05288 REV. ECN NO. Issue Date Orig.
PAGE 32
CY7C1471V33 CY7C1473V33 CY7C1475V33 Document Title: CY7C1471V33/CY7C1473V33/CY7C1475V33, 72-Mbit (2M x 36/4M x 18/1M x 72) Flow-Through SRAM with NoBL™ Architecture Document Number: 38-05288 REV. ECN NO. Issue Date Orig. of Change Description of Change *I 472335 See ECN VKN Corrected the typo in the pin configuration for 209-Ball FBGA pinout (Corrected the ball name for H9 to VSS from VSSQ). Added the Maximum Rating for Supply Voltage on VDDQ Relative to GND.