Static RAM Specification Sheet

ManualsBrandsCypress ManualsComputer HardwareCY7C150

1Kx4 Static RAM

CY7C150

Cypress Semiconductor Corporation • 3901 North First Street • San Jose • CA 95134 • 408-943-2600

Document #: 38-05024 Rev. ** Revised August 24, 2001

Features

• Memory reset function

• 1024 x 4 static RAM for control store in high-speed com-

puters

• CMOS for optimum speed/power

• High speed

— 10 ns (commercial)

— 12 ns (military)

• Low power

— 495 mW (commercial)

— 550 mW (military)

• Separate inputs and outputs

• 5-volt power supply ±10% tolerance in both commercial

and military

• Capable of withstanding greater than 2001V static dis-

charge

• TTL-compatible inputs and outputs

Functional Description

The CY7C150 is a high-performance CMOS static RAM de-

signed for use in cache memory, high-speed graphics, and

data-acquisition applications. The CY7C150 has a memory re-

set feature that allows the entire memory to be reset in two

memory cycles.

Separate I/O paths eliminates the need to multiplex data in

and data out, providing for simpler board layout and faster sys-

tem performance. Outputs are three-stated during write, reset,

deselect, or when output enable (OE

) is held HIGH, allowing

for easy memory expansion.

Reset is initiated by selecting the device (CS

= LOW) and tak-

ing the reset (RS

) input LOW. Within two memory cycles all

bits are internally cleared to zero. Since chip select must be

LOW for the device to be reset, a global reset signal can be

employed, with only selected devices being cleared at any giv-

en time.

Writing to the device is accomplished when the chip select

(CS

) and write enable (WE) inputs are both LOW. Data on the

four data inputs (D

−D

) is written into the memory location

specified on the address pins (A

through A

Reading the device is accomplished by taking chip select (CS)

and output enable (OE

) LOW while write enable (WE) remains

HIGH. Under these conditions, the contents of the memory

location specified on the address pins will appear on the four

output pins (O

through O

The output pins remain in high-impedance state when chip

enable (CE

) or output enable (OE) is HIGH, or write enable

(WE

) or reset (RS) is LOW.

A die coat is used to insure alpha immunity.

Logic Block Diagram

PinConfiguration

C150–1

64x 64

ARRA

COLUMNDECODER

ROW DECODER

SENSE AMPS

DATAINPUT

CONTROL

COLUMN

DECODER

Top View

DIP/SOIC

7C150

C150-2

GND

Selection Guide

7C150−10 7C150−12 7C150−15 7C150−25 7C150−35

Maximum Access Time (ns) Commercial 10 12 15 25

Military 12 15 25 35

Maximum Operating Current (mA) Commercial 90 90 90 90 90

Military 100 100 100 100

WWW.100Y.COM.TW WWW.100Y.COM.TW WWW.100Y.COM.TW

Summary of content (11 pages)

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Document #: 38-05024 Rev. ** OUTPUT SOURCE CURRENT (mA) OUTPUT SINK CURRENT (mA) NORMALIZED ICC SB NORMALIZED I,CC I NORMALIZED t AA DELTA tAA (ns) NORMALIZED I PO NORMALIZED t AA NORMALIZED I,CC I SB . WW 00Y.CO .TW W.1 Y.COM W WW 00Y.CO .TW W W M .1 M.T .100 W.1 Y.COM W WW 00Y.CO .TW W W WW 00Y.CO .TW W .T 00 W.1 Y.COM W M .1 W.1 Y.COM W O W W W C . W .T W 00 W WW .100Y M.T .100 W.1 Y.COM W M.T O W CY7C150 O W W C . W .T WW .100Y .TW 100 WW .100Y.C M.TW M . M O W O W O W WW .100Y.C M.TW WW .
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