DDR-II SRAM 2-Word Burst Architecture Specification Sheet

ManualsBrandsCypress ManualsComputer HardwareCY7C1520JV18

72-Mbit DDR-II SRAM 2-Word

Burst Architecture

CY7C1516JV18, CY7C1527JV18

CY7C1518JV18, CY7C1520JV18

Cypress Semiconductor Corporation • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600

Document Number: 001-12559 Rev. *D Revised June 25, 2008

Features

■ 72-Mbit density (8M x 8, 8M x 9, 4M x 18, 2M x 36)

■ 300 MHz clock for high bandwidth

■ 2-word burst for reducing address bus frequency

■ Double Data Rate (DDR) interfaces

(data transferred at 600 MHz) at 300 MHz

■ Two input clocks (K and K) for precise DDR timing

❐ SRAM uses rising edges only

■ Two input clocks for output data (C and C) to minimize clock

skew and flight time mismatches

■ Echo clocks (CQ and CQ) simplify data capture in high speed

systems

■ Synchronous internally self-timed writes

■ DDR-II operates with 1.5 cycle read latency when Delay Lock

Loop (DLL) is enabled

■ Operates similar to a DDR-I device with 1 cycle read latency in

DLL off mode

■ 1.8V core power supply with HSTL inputs and outputs

■ Variable drive HSTL output buffers

■ Expanded HSTL output voltage (1.4V–V

)

■ Available in 165-ball FBGA package (15 x 17 x 1.4 mm)

■ Offered in both Pb-free and non Pb-free packages

■ JTAG 1149.1 compatible test access port

■ Delay Lock Loop (DLL) for accurate data placement

Configurations

CY7C1516JV18 – 8M x 8

CY7C1527JV18 – 8M x 9

CY7C1518JV18 – 4M x 18

CY7C1520JV18 – 2M x 36

Functional Description

The CY7C1516JV18, CY7C1527JV18, CY7C1518JV18, and

CY7C1520JV18 are 1.8V Synchronous Pipelined SRAM

equipped with DDR-II architecture. The DDR-II consists of an

SRAM core with advanced synchronous peripheral circuitry and

a 1-bit burst counter. Addresses for read and write are latched

on alternate rising edges of the input (K) clock. Write data is

registered on the rising edges of both K and K

. Read data is

driven on the rising edges of C and C

if provided, or on the rising

edge of K and K

if C/C are not provided. Each address location

is associated with two 8-bit words in the case of CY7C1516JV18

and two 9-bit words in the case of CY7C1527JV18 that burst

sequentially into or out of the device. The burst counter always

starts with a “0” internally in the case of CY7C1516JV18 and

CY7C1527JV18. On CY7C1518JV18 and CY7C1520JV18, the

burst counter takes in the least significant bit of the external

address and bursts two 18-bit words in the case of

CY7C1518JV18 and two 36-bit words in the case of

CY7C1520JV18 sequentially into or out of the device.

Asynchronous inputs include an output impedance matching

input (ZQ). Synchronous data outputs (Q, sharing the same

physical pins as the data inputs D) are tightly matched to the two

output echo clocks CQ/CQ

, eliminating the need for separately

capturing data from each individual DDR SRAM in the system

design. Output data clocks (C/C) enable maximum system

clocking and data synchronization flexibility.

All synchronous inputs pass through input registers controlled by

the K or K

input clocks. All data outputs pass through output

registers controlled by the C or C

(or K or K in a single clock

domain) input clocks. Writes are conducted with on-chip

synchronous self-timed write circuitry.

Selection Guide

Description 300 MHz 250 MHz Unit

Maximum Operating Frequency 300 250 MHz

Maximum Operating Current x8 1035 800 mA

x9 1035 800

x18 1045 800

x36 1055 900

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Summary of content (26 pages)

PAGE 1
CY7C1516JV18, CY7C1527JV18 CY7C1518JV18, CY7C1520JV18 72-Mbit DDR-II SRAM 2-Word Burst Architecture Features Functional Description ■ 72-Mbit density (8M x 8, 8M x 9, 4M x 18, 2M x 36) ■ 300 MHz clock for high bandwidth ■ 2-word burst for reducing address bus frequency ■ Double Data Rate (DDR) interfaces (data transferred at 600 MHz) at 300 MHz ■ Two input clocks (K and K) for precise DDR timing ❐ SRAM uses rising edges only ■ Two input clocks for output data (C and C) to minimize clock skew a
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CY7C1516JV18, CY7C1527JV18 CY7C1518JV18, CY7C1520JV18 Logic Block Diagram (CY7C1516JV18) Write Reg DOFF Read Add. Decode CLK Gen. K 4M x 8 Array K Write Reg 4M x 8 Array Address Register LD Write Add. Decode 22 A(21:0) 8 Output Logic Control R/W C Read Data Reg. C 16 VREF 8 Control Logic R/W Reg. 8 NWS[1:0] CQ Reg. 8 Reg. CQ 8 8 DQ[7:0] Logic Block Diagram (CY7C1527JV18) Write Reg K CLK Gen. DOFF 9 Output Logic Control R/W C Read Data Reg. C 18 VREF R/W Read Add.
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CY7C1516JV18, CY7C1527JV18 CY7C1518JV18, CY7C1520JV18 Logic Block Diagram (CY7C1518JV18) Burst Logic 22 Write Reg 21 A(21:1) K CLK Gen. K DOFF 2M x 18 Array Address Register Write Reg 2M x 18 Array LD Write Add. Decode A(21:0) Read Add. Decode A0 18 Output Logic Control R/W C Read Data Reg. C 36 VREF 18 Control Logic R/W Reg. 18 BWS[1:0] CQ Reg. 18 CQ 18 18 Reg. DQ[17:0] Logic Block Diagram (CY7C1520JV18) Burst Logic 21 Write Reg 20 A(20:1) K K CLK Gen.
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CY7C1516JV18, CY7C1527JV18 CY7C1518JV18, CY7C1520JV18 Pin Configuration The pin configuration for CY7C1516JV18, CY7C1527JV18, CY7C1518JV18, and CY7C1520JV18 follow. [1] 165-Ball FBGA (15 x 17 x 1.
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CY7C1516JV18, CY7C1527JV18 CY7C1518JV18, CY7C1520JV18 Pin Configuration The pin configuration for CY7C1516JV18, CY7C1527JV18, CY7C1518JV18, and CY7C1520JV18 follow. [1] (continued) 165-Ball FBGA (15 x 17 x 1.
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CY7C1516JV18, CY7C1527JV18 CY7C1518JV18, CY7C1520JV18 Pin Definitions Pin Name IO Pin Description DQ[x:0] Input Output- Data Input Output Signals. Inputs are sampled on the rising edge of K and K clocks during valid write Synchronous operations. These pins drive out the requested data when the read operation is active. Valid data is driven out on the rising edge of both the C and C clocks during read operations or K and K when in single clock mode.
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CY7C1516JV18, CY7C1527JV18 CY7C1518JV18, CY7C1520JV18 Pin Definitions Pin Name (continued) IO Pin Description CQ Output Clock CQ is Referenced with Respect to C. This is a free running clock and is synchronized to the input clock for output data (C) of the DDR-II. In the single clock mode, CQ is generated with respect to K. The timing for the echo clocks is shown in the AC Timing table. CQ Output Clock CQ is Referenced with Respect to C.
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CY7C1516JV18, CY7C1527JV18 CY7C1518JV18, CY7C1520JV18 Functional Overview The CY7C1516JV18, CY7C1527JV18, CY7C1518JV18, and CY7C1520JV18 are synchronous pipelined Burst SRAMs equipped with a DDR interface, which operates with a read latency of one and a half cycles when DOFF pin is tied HIGH. When DOFF pin is set LOW or connected to VSS the device behaves in DDR-I mode with a read latency of one clock cycle. Accesses are initiated on the rising edge of the positive input clock (K).
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CY7C1516JV18, CY7C1527JV18 CY7C1518JV18, CY7C1520JV18 Depth Expansion Depth expansion requires replicating the LD control signal for each bank. All other control signals can be common between banks as appropriate. Programmable Impedance An external resistor, RQ, must be connected between the ZQ pin on the SRAM and VSS to allow the SRAM to adjust its output driver impedance. The value of RQ must be 5x the value of the intended line impedance driven by the SRAM.
PAGE 10
CY7C1516JV18, CY7C1527JV18 CY7C1518JV18, CY7C1520JV18 Truth Table The truth table for the CY7C1516JV18, CY7C1527JV18, CY7C1518JV18, and CY7C1520JV18 follows. [2, 3, 4, 5, 6, 7] Operation K LD R/W Write Cycle: Load address; wait one cycle; input write data on consecutive K and K rising edges. L-H L L D(A1) at K(t + 1) ↑ D(A2) at K(t + 1) ↑ Read Cycle: Load address; wait one and a half cycle; read data on consecutive C and C rising edges.
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CY7C1516JV18, CY7C1527JV18 CY7C1518JV18, CY7C1520JV18 Write Cycle Descriptions The write cycle description table for CY7C1527JV18 follows. [2, 8] BWS0 K K Comments L L–H – During the data portion of a write sequence, the single byte (D[8:0]) is written into the device. L – L–H During the data portion of a write sequence, the single byte (D[8:0]) is written into the device. H L–H – No data is written into the device during this portion of a write operation.
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CY7C1516JV18, CY7C1527JV18 CY7C1518JV18, CY7C1520JV18 IEEE 1149.1 Serial Boundary Scan (JTAG) These SRAMs incorporate a serial boundary scan Test Access Port (TAP) in the FBGA package. This part is fully compliant with IEEE Standard #1149.1-2001. The TAP operates using JEDEC standard 1.8V IO logic levels. Disabling the JTAG Feature It is possible to operate the SRAM without using the JTAG feature. To disable the TAP controller, TCK must be tied LOW (VSS) to prevent clocking of the device.
PAGE 13
CY7C1516JV18, CY7C1527JV18 CY7C1518JV18, CY7C1520JV18 IDCODE The IDCODE instruction loads a vendor-specific, 32-bit code into the instruction register. It also places the instruction register between the TDI and TDO pins and shifts the IDCODE out of the device when the TAP controller enters the Shift-DR state. The IDCODE instruction is loaded into the instruction register at power up or whenever the TAP controller is given a Test-Logic-Reset state.
PAGE 14
CY7C1516JV18, CY7C1527JV18 CY7C1518JV18, CY7C1520JV18 TAP Controller State Diagram The state diagram for the TAP controller follows. [9] 1 TEST-LOGIC RESET 0 0 TEST-LOGIC/ IDLE 1 SELECT DR-SCAN 1 1 SELECT IR-SCAN 0 0 1 1 CAPTURE-DR CAPTURE-IR 0 0 SHIFT-DR 0 SHIFT-IR 1 1 EXIT1-DR 1 EXIT1-IR 0 1 0 PAUSE-DR 0 PAUSE-IR 1 0 1 0 EXIT2-DR 0 EXIT2-IR 1 1 UPDATE-IR UPDATE-DR 1 0 0 1 0 Note 9. The 0/1 next to each state represents the value at TMS at the rising edge of TCK.
PAGE 15
CY7C1516JV18, CY7C1527JV18 CY7C1518JV18, CY7C1520JV18 TAP Controller Block Diagram 0 Bypass Register 2 Selection Circuitry TDI 1 0 Selection Circuitry Instruction Register 31 30 29 . . 2 1 0 1 0 TDO Identification Register 108 . . . . 2 Boundary Scan Register TCK TAP Controller TMS TAP Electrical Characteristics Over the Operating Range [10, 11, 12] Parameter Description Test Conditions Min Max Unit VOH1 Output HIGH Voltage IOH = −2.0 mA 1.
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CY7C1516JV18, CY7C1527JV18 CY7C1518JV18, CY7C1520JV18 TAP AC Switching Characteristics Over the Operating Range [13, 14] Parameter Description Min Max Unit 20 MHz tTCYC TCK Clock Cycle Time tTF TCK Clock Frequency tTH TCK Clock HIGH 20 ns tTL TCK Clock LOW 20 ns tTMSS TMS Setup to TCK Clock Rise 5 ns tTDIS TDI Setup to TCK Clock Rise 5 ns tCS Capture Setup to TCK Rise 5 ns tTMSH TMS Hold after TCK Clock Rise 5 ns tTDIH TDI Hold after Clock Rise 5 ns tCH Capture Hold a
PAGE 17
CY7C1516JV18, CY7C1527JV18 CY7C1518JV18, CY7C1520JV18 Identification Register Definitions Instruction Field Value CY7C1516JV18 CY7C1527JV18 CY7C1518JV18 CY7C1520JV18 000 000 000 000 Revision Number (31:29) Cypress Device ID (28:12) Cypress JEDEC ID (11:1) Description Version number. 11010100010000100 11010100010001100 11010100010010100 11010100010100100 Defines the type of SRAM.
PAGE 18
CY7C1516JV18, CY7C1527JV18 CY7C1518JV18, CY7C1520JV18 Boundary Scan Order Bit # Bump ID Bit # Bump ID Bit # Bump ID Bit # Bump ID 0 6R 28 10G 56 6A 84 1J 1 6P 29 9G 57 5B 85 2J 2 6N 30 11F 58 5A 86 3K 3 7P 31 11G 59 4A 87 3J 4 7N 32 9F 60 5C 88 2K 5 7R 33 10F 61 4B 89 1K 6 8R 34 11E 62 3A 90 2L 7 8P 35 10E 63 2A 91 3L 8 9R 36 10D 64 1A 92 1M 9 11P 37 9E 65 2B 93 1L 10 10P 38 10C 66 3B 94 3N 3M 11 10N 39 11D 6
PAGE 19
CY7C1516JV18, CY7C1527JV18 CY7C1518JV18, CY7C1520JV18 Power Up Sequence in DDR-II SRAM DDR-II SRAMs must be powered up and initialized in a predefined manner to prevent undefined operations. Power Up Sequence ■ Apply power and drive DOFF either HIGH or LOW (all other inputs can be HIGH or LOW). ❐ Apply VDD before VDDQ. ❐ Apply VDDQ before VREF or at the same time as VREF. ❐ Drive DOFF HIGH. ■ Provide stable DOFF (HIGH), power and clock (K, K) for 1024 cycles to lock the DLL.
PAGE 20
CY7C1516JV18, CY7C1527JV18 CY7C1518JV18, CY7C1520JV18 Maximum Ratings Current into Outputs (LOW) ........................................ 20 mA Exceeding maximum ratings may impair the useful life of the device. These user guidelines are not tested. Storage Temperature ................................. –65°C to +150°C Static Discharge Voltage (MIL-STD-883, M 3015).... >2001V Latch Up Current ....................................................
PAGE 21
CY7C1516JV18, CY7C1527JV18 CY7C1518JV18, CY7C1520JV18 AC Electrical Characteristics Over the Operating Range [11] Parameter Description Test Conditions Min Typ Max Unit VIH Input HIGH Voltage VREF + 0.2 – – V VIL Input LOW Voltage – – VREF – 0.2 V Capacitance Tested initially and after any design or process change that may affect these parameters.
PAGE 22
CY7C1516JV18, CY7C1527JV18 CY7C1518JV18, CY7C1520JV18 Switching Characteristics Over the Operating Range [20] Cypress Consortium Parameter Parameter 300 MHz Description Min Max Min Max VDD(Typical) to the first Access [22] tPOWER 250 MHz 1 – 1 – Unit ms tCYC tKHKH K Clock and C Clock Cycle Time 3.3 8.4 4.0 8.4 ns tKH tKHKL Input Clock (K/K and C/C) HIGH 1.32 – 1.6 – ns tKL tKLKH Input Clock (K/K and C/C) LOW 1.32 – 1.
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CY7C1516JV18, CY7C1527JV18 CY7C1518JV18, CY7C1520JV18 Switching Waveforms Figure 5. Read/Write/Deselect Sequence [26, 27, 28] READ 2 NOP 1 READ 3 NOP 4 NOP 5 WRITE 6 WRITE 7 READ 8 A3 A4 9 10 K tKH tKL tKHKH tCYC K LD tSC tHC R/W A A0 tSA A2 A1 tHD tHA tHD tSD DQ Q00 t KHCH t CLZ Q01 Q10 Q11 tSD D20 D21 D30 D31 Q40 Q41 t CQDOH t CHZ tDOH tCO t CQD C t KHCH tKH tKL tCYC tKHKH C# tCQOH tCCQO CQ tCQOH tCCQO tCQH tCQHCQH CQ# DON’T CARE UNDEFINED Notes 26.
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CY7C1516JV18, CY7C1527JV18 CY7C1518JV18, CY7C1520JV18 Ordering Information Not all of the speed, package, and temperature ranges are available. Please contact your local sales representative or visit www.cypress.com for actual products offered. Speed (MHz) 300 Ordering Code CY7C1516JV18-300BZC Package Diagram Package Type 51-85195 165-Ball Fine Pitch Ball Grid Array (15 x 17 x 1.
PAGE 25
CY7C1516JV18, CY7C1527JV18 CY7C1518JV18, CY7C1520JV18 Package Diagram Figure 6. 165-Ball FBGA (15 x 17 x 1.40 mm), 51-85195 "/44/- 6)%7 4/0 6)%7 - # ! " 0). #/2.%2 - # 0). #/2.%2 8 ! " " # # ! $ $ & & ' ' ( * % ¼ % ( * + , , + - - . . 0 0 2 2 ! " ¼ .
PAGE 26
CY7C1516JV18, CY7C1527JV18 CY7C1518JV18, CY7C1520JV18 Document History Page Document Title: CY7C1516JV18/CY7C1527JV18/CY7C1518JV18/CY7C1520JV18, 72-Mbit DDR-II SRAM 2-Word Burst Architecture Document Number: 001-12559 REV. ECN NO. ISSUE DATE ORIG.