Flexible USB NAND Flash Controller Specification Sheet

ManualsBrandsCypress ManualsComputer HardwareCY7C68033

EZ-USB NX2LP-Flex™ Flexible USB NAND Flash Controller

CY7C68033/CY7C68034

Cypress Semiconductor Corporation • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600

Document #: 001-04247 Rev. *D Revised September 21, 2006

CY7C68033/CY7C68034 Silicon Features

• Certified compliant for Bus- or Self-powered USB 2.0

operation (TID# 40490118)

• Single-chip, integrated USB 2.0 transceiver and smart SIE

• Ultra low power – 43 mA typical current draw in any mode

• Enhanced 8051 core

— Firmware runs from internal RAM, which is downloaded

from NAND flash at startup

— No external EEPROM required

• 15 KBytes of on-chip Code/Data RAM

— Default NAND firmware ~8 kB

— Default free space ~7 kB

• Four programmable BULK/INTERRUPT/ISOCHRONOUS

endpoints

— Buffering options: double, triple, and quad

• Additional programmable (BULK/INTERRUPT) 64-byte

endpoint

• SmartMedia Standard Hardware ECC generation with 1-bit

correction and 2-bit detection

• GPIF (General Programmable Interface)

— Allows direct connection to most parallel interfaces

— Programmable waveform descriptors and configuration

registers to define waveforms

— Supports multiple Ready (RDY) inputs and Control (CTL)

outputs

• 12 fully-programmable GPIO pins

• Integrated, industry-standard enhanced 8051

— 48-MHz, 24-MHz, or 12-MHz CPU operation

— Four clocks per instruction cycle

— Three counter/timers

— Expanded interrupt system

— Two data pointers

• 3.3V operation with 5V tolerant inputs

• Vectored USB interrupts and GPIF/FIFO interrupts

• Separate data buffers for the Set-up and Data portions of a

CONTROL transfer

• Integrated I

C™ controller, runs at 100 or 400 kHz

• Four integrated FIFOs

— Integrated glue logic and FIFOs lower system cost

— Automatic conversion to and from 16-bit buses

— Master or slave operation

— Uses external clock or asynchronous strobes

— Easy interface to ASIC and DSP ICs

• Available in space saving, 56-pin QFN package

CY7C68034 Only Silicon Features:

• Ideal for battery powered applications

— Suspend current: 100 μA (typ.)

CY7C68033 Only Silicon Features:

• Ideal for non-battery powered applications

— Suspend current: 300 μA (typ.)

x20

PLL

/0.5

/1.0

/2.0

8051 Core

12/24/48 MHz,

four clocks/cycle

1.5k

D+

D–

Address (16)/Data Bus (8)

GPIF

Smart

USB

1.1/2.0

Engine

USB

2.0

XCVR

Additional I/Os

CTL (3)

RDY (2)

8/16

ECC

NAND

Boot Logic

(ROM)

NX2LP-Flex

24 MHz

Ext. Xtal

Connected for

full-speed USB

Integrated full- and

high-speed XCVR

15 kB

RAM

General Programmable

I/F to ASIC/DSP or bus

standards such as 8-bit

NAND, EPP, etc.

4 kB

FIFO

Up to 96 MB/s burst rate

High-performance,

enhanced 8051 core

with low power options

‘Soft Configuration’ enables

easy firmware changes

FIFO and USB endpoint memory

(master or slave modes)

Enhanced USB core

simplifies 8051 code

Master

Block Diagram

[+] Feedback

Summary of content (33 pages)

PAGE 1
CY7C68033/CY7C68034 EZ-USB NX2LP-Flex™ Flexible USB NAND Flash Controller CY7C68033/CY7C68034 Silicon Features • Integrated, industry-standard enhanced 8051 • Certified compliant for Bus- or Self-powered USB 2.0 operation (TID# 40490118) • Single-chip, integrated USB 2.
PAGE 2
CY7C68033/CY7C68034 Default NAND Firmware Features Because the NX2LP-Flex™ is intended for NAND Flash-based USB mass storage applications, a default firmware image is included in the development kit with the following features: • High (480-Mbps) or full (12-Mbps) speed USB support • Both common NAND page sizes supported — 512 bytes for up to 1 Gb capacity — 2K bytes for up to 8 Gb capacity • 12 configurable general-purpose I/O (GPIO) pins — 2 dedicated chip enable (CE#) pins — 6 configurable CE#/GPIO pins
PAGE 3
CY7C68033/CY7C68034 Figure 1. Example DVB Block Diagram The 8051 microprocessor embedded in the NX2LP-Flex has 256 bytes of register RAM, an expanded interrupt system and three timer/counters. Buttons 8051 Clock Frequency I/O NAND-Based DVB Unit LCD I/O CTL NX2LPFlex D+/- CE[7:0] NAND Bank(s) I/O I/O DVB Decoder Audio / Video I/O Figure 2.
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CY7C68033/CY7C68034 Table 1.
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CY7C68033/CY7C68034 Figure 4. NX2LP-Flex Enumeration Sequence Start-up Yes NAND Flash Present? No values stored in ROM space. The default silicon ID values should only be used for development purposes. Cypress requires designers to use their own Vendor ID for final products. A Vendor ID is obtained through registration with the USB Implementor’s Forum (USB-IF).
PAGE 6
CY7C68033/CY7C68034 Table 3.
PAGE 7
CY7C68033/CY7C68034 Table 4.
PAGE 8
CY7C68033/CY7C68034 Table 5. Reset Timing Values Condition Power-on Reset with crystal Power-on Reset with external clock source Powered Reset Figure 6. Internal Code Memory TRESET FFFF 5 ms 200 μs + Clock stability time E200 E1FF 200 μs E000 7.5 kBytes USB registers and 4 kBytes FIFO buffers (RD#, WR#) 512 Bytes RAM Data (RD#, WR#)* Wakeup Pins The 8051 puts itself and the rest of the chip into a power-down mode by setting PCON.0 = 1. This stops the oscillator and PLL.
PAGE 9
CY7C68033/CY7C68034 Endpoint RAM Setup Data Buffer Size • 3 × 64 bytes (Endpoints 0 and 1) • 8 × 512 bytes (Endpoints 2, 4, 6, 8) A separate 8-byte buffer at 0xE6B8-0xE6BF holds the setup data from a CONTROL transfer. Endpoint Configurations (High-speed Mode) Organization • EP0 — Bidirectional endpoint zero, 64-byte buffer • EP1IN, EP1OUT — 64-byte buffers, bulk or interrupt • EP2,4,6,8 — Eight 512-byte buffers, bulk, interrupt, or isochronous.
PAGE 10
CY7C68033/CY7C68034 Table 6. Default Full-Speed Alternate Settings[2, 3] (continued) ep4 0 64 bulk out (2×) 64 bulk out (2×) 64 bulk out (2×) ep6 0 64 bulk in (2×) 64 int in (2×) 64 iso in (2×) ep8 0 64 bulk in (2×) 64 bulk in (2×) 64 bulk in (2×) Default High-Speed Alternate Settings Table 7.
PAGE 11
CY7C68033/CY7C68034 the default NAND firmware image implements an 8-bit data bus and up to 8 chip enable pins on the GPIF ports, it is recommended that designs based upon the default firmware image use an 8-bit data bus as well. Each GPIF vector defines the state of the control outputs, and determines what state a ready input (or multiple inputs) must be before proceeding. The GPIF vector can be programmed to advance a FIFO to the next data value, advance an address, etc.
PAGE 12
CY7C68033/CY7C68034 Pin Assignments Figure 9 and Figure 10 identify all signals for the 56-pin NX2LP-Flex package. Three modes of operation are available for the NX2LP-Flex: Port mode, GPIF Master mode, and Slave FIFO mode. These modes define the signals on the right edge of each column in Figure 9. The right-most column details the signal functionality from the default NAND firmware image, which actually utilizes GPIF Master mode.
PAGE 13
CY7C68033/CY7C68034 Figure 10.
PAGE 14
CY7C68033/CY7C68034 Table 8. NX2LP-Flex Pin Descriptions [6] 56 QFN Default Pin Pin Name Number NAND Firmware Usage Pin Type Default State Description 9 DMINUS N/A I/O/Z Z USB D– Signal. Connect to the USB D– signal. 8 DPLUS N/A I/O/Z Z USB D+ Signal. Connect to the USB D+ signal. 42 RESET# N/A Input N/A Active LOW Reset. Resets the entire chip. See section ”Reset and Wakeup” on page 7 for more details. 5 XTALIN N/A Input N/A Crystal Input.
PAGE 15
CY7C68033/CY7C68034 Table 8. NX2LP-Flex Pin Descriptions (continued)[6] 56 QFN Default Pin Pin Name Number NAND Firmware Usage Pin Type Default State GPIO8 I/O/Z I Description 13 GPIO8 GPIO8: is a bidirectional IO port pin. 14 Reserved# N/A Input N/A 15 SCL N/A OD Z Clock for the I2C interface. Connect to VCC with a 2.2K resistor, even if no I2C peripheral is attached. 16 SDATA N/A OD Z Data for the I2C interface. Connect to VCC with a 2.
PAGE 16
CY7C68033/CY7C68034 Table 8. NX2LP-Flex Pin Descriptions (continued)[6] 56 QFN Default Pin Pin Name Number NAND Firmware Usage Pin Type Default State Description 39 PA6 or PKTEND GPIO0 (Input) I/O/Z I (PA6) Multiplexed pin whose function is selected by the IFCONFIG[1:0] bits. PA6 is a bidirectional I/O port pin. PKTEND is an input used to commit the FIFO packet data to the endpoint and whose polarity is programmable via FIFOPINPOLAR[5]. GPIO1 is a general purpose I/O signal.
PAGE 17
CY7C68033/CY7C68034 Table 8. NX2LP-Flex Pin Descriptions (continued)[6] 56 QFN Default Pin Pin Name Number NAND Firmware Usage Pin Type Default State Description 46 PD1 or FD[9] CE1# I/O/Z I (PD1) Multiplexed pin whose function is selected by the IFCONFIG[1:0] and EPxFIFOCFG.0 (wordwide) bits. FD[9] is the bidirectional FIFO/GPIF data bus. CE1# is a NAND chip enable output signal.
PAGE 18
CY7C68033/CY7C68034 Register Summary NX2LP-Flex register bit definitions are described in the EZ-USB TRM in greater detail. Some registers that are listed here and in the TRM do not apply to the NX2LP-Flex. They are kept here for consistency reasons only. Registers that do not apply to the NX2LP-Flex should be left at their default power-up values. Table 9.
PAGE 19
CY7C68033/CY7C68034 Table 9. NX2LP-Flex Register Summary (continued) Hex E629 E62A E62B E62C E62D E62E E62F E630 H.S. E630 F.S. E631 H.S. E631 F.S E632 H.S. E632 F.S E633 H.S. E633 F.S E634 H.S. E634 F.S E635 H.S. E635 F.S E636 H.S. E636 F.S E637 H.S. E637 F.
PAGE 20
CY7C68033/CY7C68034 Table 9.
PAGE 21
CY7C68033/CY7C68034 Table 9.
PAGE 22
CY7C68033/CY7C68034 Table 9.
PAGE 23
CY7C68033/CY7C68034 Table 9.
PAGE 24
CY7C68033/CY7C68034 Table 9.
PAGE 25
CY7C68033/CY7C68034 DC Characteristics Table 10.DC Characteristics Parameter VCC Description Conditions Supply Voltage VCC Ramp Up 0 to 3.3V Min. Typ. Max. 3.00 3.3 3.60 Unit V μs 200 VIH Input HIGH Voltage 2 5.25 V VIL Input LOW Voltage –0.5 0.8 V VIH_X Crystal Input HIGH Voltage 2 5.25 V VIL_X Crystal Input LOW Voltage –0.5 0.
PAGE 26
CY7C68033/CY7C68034 Slave FIFO Asynchronous Read Figure 11. Slave FIFO Asynchronous Read Timing Diagram[13] tRDpwh SLRD tRDpwl FLAGS tXFD tXFLG DATA N+1 N tOEon tOEoff SLOE Table 11.Slave FIFO Asynchronous Read Parameters[15] Parameter Description Min. Max. Unit tRDpwl SLRD Pulse Width LOW 50 ns tRDpwh SLRD Pulse Width HIGH 50 ns tXFLG SLRD to FLAGS Output Propagation Delay 70 ns tXFD SLRD to FIFO Data Output Propagation Delay 15 ns tOEon SLOE Turn-on to FIFO Data Valid 10.
PAGE 27
CY7C68033/CY7C68034 Slave FIFO Asynchronous Packet End Strobe Figure 13. Slave FIFO Asynchronous Packet End Strobe Timing Diagram[9] tPEpwh PKTEND tPEpwl FLAGS tXFLG Table 13.Slave FIFO Asynchronous Packet End Strobe Parameters[15] Parameter Description Min. tPEpwl PKTEND Pulse Width LOW 50 tPWpwh PKTEND Pulse Width HIGH 50 tXFLG PKTEND to FLAGS Output Propagation Delay Max. Unit ns ns 115 ns Max. Unit Slave FIFO Output Enable Figure 14.
PAGE 28
CY7C68033/CY7C68034 Slave FIFO Asynchronous Address Figure 16. Slave FIFO Asynchronous Address Timing Diagram[13] SLCS/FIFOADR [1:0] tFAH tSFA SLRD/SLWR/PKTEND Table 16.Slave FIFO Asynchronous Address Parameters[15] Parameter Description Min. Max. Unit tSFA FIFOADR[1:0] to SLRD/SLWR/PKTEND Setup Time 10 ns tFAH RD/WR/PKTEND to FIFOADR[1:0] Hold Time 10 ns Sequence Diagram Sequence Diagram of a Single and Burst Asynchronous Read Figure 17.
PAGE 29
CY7C68033/CY7C68034 Figure 17 diagrams the timing relationship of the SLAVE FIFO signals during an asynchronous FIFO read. It shows a single read followed by a burst read. • At t = 0 the FIFO address is stable and the SLCS signal is asserted. • At t = 1, SLOE is asserted. This results in the data bus being driven. The data that is driven on to the bus is previous data, it data that was in the FIFO from a prior read cycle. • At t = 2, SLRD is asserted.
PAGE 30
CY7C68033/CY7C68034 Ordering Information Table 17.Ordering Information Ordering Code Description Silicon for battery-powered applications CY7C68034-56LFXC 8x8 mm, 56 QFN – Lead-free Silicon for non-battery-powered applications CY7C68033-56LFXC 8x8 mm, 56 QFN – Lead-free Development Kit CY3686 EZ-USB NX2LP-Flex Development Kit Package Diagram Figure 20. 56-Lead QFN 8 x 8 mm LF56A DIMENSIONS IN MM[INCHES] MIN. MAX. REFERENCE JEDEC MO-220 TOP VIEW SIDE VIEW 7.90[0.311] 8.10[0.319] A 0.08[0.
PAGE 31
CY7C68033/CY7C68034 PCB Layout Recommendations[16] The following recommendations should be followed to ensure reliable high-performance operation: • At least a four-layer impedance controlled boards is recommended to maintain signal quality. • Specify impedance targets (ask your board vendor what they can achieve) to meet USB specifications. • To control impedance, maintain trace widths and trace spacing. • Minimize any stubs to avoid reflected signals.
PAGE 32
CY7C68033/CY7C68034 Figure 22. Plot of the Solder Mask (White Area) Figure 23. X-ray Image of the Assembly Purchase of I2C components from Cypress, or one of its sublicensed Associated Companies, conveys a license under the Philips I2C Patent Rights to use these components in an I2C system, provided that the system conforms to the I2C Standard Specification as defined by Philips.
PAGE 33
CY7C68033/CY7C68034 Document History Page Document Title: CY7C68033/CY7C68034 EZ-USB NX2LP-Flex™ Flexible USB NAND Flash Controller Document #: 001-04247 Rev. *D REV. ECN NO. Issue Date Orig. of Change ** 388499 See ECN GIR Preliminary draft *A 394699 See ECN XUT Minor Change: Upload data sheet to external website. Publicly announcing the parts. No physical changes to document were made *B 400518 See ECN GIR Took ‘Preliminary’ off the top of all pages. Corrected the first bulleted item.