Flexible USB NAND Flash Controller Specification Sheet

CY7C68033/CY7C68034
Document #: 001-04247 Rev. *D Page 11 of 33
the default NAND firmware image implements an 8-bit data
bus and up to 8 chip enable pins on the GPIF ports, it is recom-
mended that designs based upon the default firmware image
use an 8-bit data bus as well.
Each GPIF vector defines the state of the control outputs, and
determines what state a ready input (or multiple inputs) must
be before proceeding. The GPIF vector can be programmed
to advance a FIFO to the next data value, advance an address,
etc. A sequence of the GPIF vectors make up a single
waveform that will be executed to perform the desired data
move between the NX2LP-Flex and the external device.
Three Control OUT Signals
The NX2LP-Flex exposes three control signals, CTL[2:0].
CTLx waveform edges can be programmed to make transi-
tions as fast as once per clock (20.8 ns using a 48-MHz clock).
Two Ready IN Signals
The 8051 programs the GPIF unit to test the RDY pins for
GPIF branching. The 56-pin package brings out two signals,
RDY[1:0].
Long Transfer Mode
In GPIF Master mode, the 8051 appropriately sets GPIF trans-
action count registers (GPIFTCB3, GPIFTCB2, GPIFTCB1, or
GPIFTCB0) for unattended transfers of up to 2
32
transactions.
The GPIF automatically throttles data flow to prevent under- or
over-flow until the full number of requested transactions
complete. The GPIF decrements the value in these registers
to represent the current status of the transaction.
ECC Generation
[5]
The NX2LP-Flex can calculate ECCs (Error-Correcting
Codes) on data that passes across its GPIF or Slave FIFO
interfaces. There are two ECC configurations:
• Two ECCs, each calculated over 256 bytes (SmartMedia
Standard)
• One ECC calculated over 512 bytes.
The two ECC configurations described below are selected by
the ECCM bit. The ECC can correct any one-bit error or detect
any two-bit error.
ECCM = 0
Two 3-byte ECCs, each calculated over a 256-byte block of
data. This configuration conforms to the SmartMedia Standard
and is used by both the NAND boot logic and default NAND
firmware image.
When any value is written to ECCRESET and data is then
passed across the GPIF or Slave FIFO interface, the ECC for
the first 256 bytes of data will be calculated and stored in
ECC1. The ECC for the next 256 bytes of data will be stored
in ECC2. After the second ECC is calculated, the values in the
ECCx registers will not change until ECCRESET is written
again, even if more data is subsequently passed across the
interface.
ECCM = 1
One 3-byte ECC calculated over a 512-byte block of data.
When any value is written to ECCRESET and data is then
passed across the GPIF or Slave FIFO interface, the ECC for
the first 512 bytes of data will be calculated and stored in
ECC1; ECC2 is unused. After the ECC is calculated, the value
in ECC1 will not change until ECCRESET is written again,
even if more data is subsequently passed across the interface
Autopointer Access
NX2LP-Flex provides two identical autopointers. They are
similar to the internal 8051 data pointers, but with an additional
feature: they can optionally increment after every memory
access. Also, the autopointers can point to any NX2LP-Flex
register or endpoint buffer space.
I
2
C Controller
NX2LP has one I
2
C port that the 8051, once running uses to
control external I
2
C devices. The I
2
C port operates in master
mode only. The I
2
C post is disabled at startup and only
available for use after the initial NAND access.
I
2
C Port Pins
The I
2
C pins SCL and SDA must have external 2.2-kΩ pull-up
resistors even if no EEPROM is connected to the NX2LP.
I
2
C Interface General-Purpose Access
The 8051 can control peripherals connected to the I
2
C bus
using the I
2
CTL and I
2
DATA registers. NX2LP provides I
2
C
master control only and is never an I
2
C slave.
Note
5. To use the ECC logic, the GPIF or Slave FIFO interface must be configured for byte-wide operation.
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