Flexible USB NAND Flash Controller Specification Sheet

CY7C68033/CY7C68034
Document #: 001-04247 Rev. *D Page 16 of 33
39 PA6 or
PKTEND
GPIO0
(Input)
I/O/Z I
(PA6)
Multiplexed pin whose function is selected by the IFCONFIG[1:0]
bits.
PA6 is a bidirectional I/O port pin.
PKTEND is an input used to commit the FIFO packet data to the
endpoint and whose polarity is programmable via FIFOPIN-
POLAR[5].
GPIO1 is a general purpose I/O signal.
40 PA7 or
FLAGD or
SLCS#
GPIO1
(Input)
I/O/Z I
(PA7)
Multiplexed pin whose function is selected by the IFCONFIG[1:0]
and PORTACFG[7] bits.
PA7 is a bidirectional I/O port pin.
FLAGD is a programmable slave-FIFO output status flag signal.
SLCS# gates all other slave FIFO enable/strobes
GPIO0 is a general purpose I/O signal.
Port B
18 PB0 or
FD[0]
DD0 I/O/Z I
(PB0)
Multiplexed pin whose function is selected by IFCONFIG[1:0].
PB0 is a bidirectional I/O port pin.
FD[0] is the bidirectional FIFO/GPIF data bus.
DD0 is a bidirectional NAND data bus signal.
19 PB1 or
FD[1]
DD1 I/O/Z I
(PB1)
Multiplexed pin whose function is selected by IFCONFIG[1:0].
PB1 is a bidirectional I/O port pin.
FD[1] is the bidirectional FIFO/GPIF data bus.
DD1 is a bidirectional NAND data bus signal.
20 PB2 or
FD[2]
DD2 I/O/Z I
(PB2)
Multiplexed pin whose function is selected by IFCONFIG[1:0].
PB2 is a bidirectional I/O port pin.
FD[2] is the bidirectional FIFO/GPIF data bus.
DD2 is a bidirectional NAND data bus signal.
21 PB3 or
FD[3]
DD3 I/O/Z I
(PB3)
Multiplexed pin whose function is selected by IFCONFIG[1:0].
PB3 is a bidirectional I/O port pin.
FD[3] is the bidirectional FIFO/GPIF data bus.
DD3 is a bidirectional NAND data bus signal.
22 PB4 or
FD[4]
DD4 I/O/Z I
(PB4)
Multiplexed pin whose function is selected by IFCONFIG[1:0].
PB4 is a bidirectional I/O port pin.
FD[4] is the bidirectional FIFO/GPIF data bus.
DD4 is a bidirectional NAND data bus signal.
23 PB5 or
FD[5]
DD5 I/O/Z I
(PB5)
Multiplexed pin whose function is selected by IFCONFIG[1:0].
PB5 is a bidirectional I/O port pin.
FD[5] is the bidirectional FIFO/GPIF data bus.
DD5 is a bidirectional NAND data bus signal.
24 PB6 or
FD[6]
DD6 I/O/Z I
(PB6)
Multiplexed pin whose function is selected by IFCONFIG[1:0].
PB6 is a bidirectional I/O port pin.
FD[6] is the bidirectional FIFO/GPIF data bus.
DD6 is a bidirectional NAND data bus signal.
25 PB7 or
FD[7]
DD7 I/O/Z I
(PB7)
Multiplexed pin whose function is selected by IFCONFIG[1:0].
PB7 is a bidirectional I/O port pin.
FD[7] is the bidirectional FIFO/GPIF data bus.
DD7 is a bidirectional NAND data bus signal.
PORT D
45 PD0 or
FD[8]
CE0# I/O/Z I
(PD0)
Multiplexed pin whose function is selected by the IFCONFIG[1:0]
and EPxFIFOCFG.0 (wordwide) bits.
FD[8] is the bidirectional FIFO/GPIF data bus.
CE0# is a NAND chip enable output signal.
Table 8. NX2LP-Flex Pin Descriptions (continued)
[6]
56 QFN
Pin
Number
Default Pin
Name
NAND
Firmware
Usage
Pin
Type
Default
State
Description
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