Nonvolatile Programmable System-on-Chip Specification Sheet

ManualsBrandsCypress ManualsComputer HardwareCY8CNP102E

PRELIMINARY

CY8CNP102B, CY8CNP102E

Nonvolatile Programmable System-on-Chip

(

PSoC® NV)

Cypress Semiconductor Corporation • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600

Document #: 001-43991 Rev. *D Revised October 20, 2008

Overview

The Cypress nonvolatile Programmable System-on-Chip

(PSoC

NV) processor combines a versatile Programmable

System-on-Chip™ (PSoC) core with an infinite endurance

nvSRAM in a single package. The PSoC NV combines an 8-bit

MCU core (M8C), configurable analog and digital functions, a

uniquely flexible IO interface, and a high density nvSRAM. This

creates versatile data logging solutions that provide value

through component integration and programmability. The flexible

core and a powerful development environment work to reduce

design complexity, component count, and development time.

Features

■ Powerful Harvard Architecture Processor

❐ M8C processor speeds

• Up to 12 MHz for 3.3V operation

• Up to 24 MHz for 5V operation

❐ Two 8x8 multiply, 32 bit accumulate

❐ Low power at high speed

■ Operating Voltage

❐ 3.3V (CY8CNP102B)

❐ 5V (CY8CNP102E)

■ Advanced Peripherals

❐ 12 Rail-to-Rail Analog PSoC blocks provide:

• Up to 14 bit ADCs

• Up to 9 bit DACs

• Programmable Gain Amplifiers

• Programmable Filters and Comparators

• 8 Analog channels for simultaneous sampling

• Up to 820 SPS for each channel with 8 channel sampling

and logging

❐ 16 Digital PSoC Blocks provide:

• 8 to 32 bit timers, counters, and PWMs

• CRC and PRS Modules

• Up to 4 Full Duplex UARTs

• Multiple SPI™ Masters and Slaves

❐ Complex Peripherals by Combining Blocks

■ Precision, Programmable Clocking

❐ Internal ±2.5% 24 and 48 MHz Oscillator

❐ 24 and 48 MHz with optional 32.768 kHz Crystal

❐ Optional External Oscillator, up to 24 MHz

❐ Internal Oscillator for Watchdog and Sleep

■ Flexible On-Chip Memory

❐ 32K Bytes Flash Program Storage

❐ 2K Bytes SRAM Data Storage

❐ 256K Bytes secure store nvSRAM with data throughput be-

tween 100 KBPS and 1 MBPS

❐ In-System Serial Programming (ISSP)

❐ Partial Flash Updates

❐ Flexible Protection Modes

❐ EEPROM Emulation in Flash

■ Programmable Pin Configurations

❐ 33 GPIOs

❐ 25 mA Sink on all GPIO

❐ Pull up, Pull down, High Z, Strong, or Open Drain Drive

Modes on all GPIO

❐ Up to 12 Analog Inputs on GPIOs

❐ Analog Outputs with 40 mA on 4 GPIOs

❐ Configurable Interrupt on all GPIOs

■ Additional System Resources

❐ I

C Slave, Master, and MultiMaster to 100 Kbps

and 400 Kbps

❐ Watchdog and Sleep Timers

❐ Integrated Supervisory Circuit

❐ On-Chip Precision Voltage Reference

■ Complete Development Tools

❐ Free Development Software (PSoC Designer™)

❐ Full Featured, In Circuit Emulator and Programmer

❐ Full Speed Emulation

❐ C Compilers, Assembler, and Linker

■ Temperature and Packaging

❐ Industrial Temperature Range: -40°C to +85°C

❐ Packaging: 100-pin TQFP

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Summary of content (38 pages)

PAGE 1
PRELIMINARY CY8CNP102B, CY8CNP102E Nonvolatile Programmable System-on-Chip (PSoC® NV) Overview ■ The Cypress nonvolatile Programmable System-on-Chip (PSoC® NV) processor combines a versatile Programmable System-on-Chip™ (PSoC) core with an infinite endurance nvSRAM in a single package. The PSoC NV combines an 8-bit MCU core (M8C), configurable analog and digital functions, a uniquely flexible IO interface, and a high density nvSRAM.
PAGE 2
PRELIMINARY CY8CNP102B, CY8CNP102E Logic Block Diagram Document #: 001-43991 Rev.
PAGE 3
PRELIMINARY CY8CNP102B, CY8CNP102E Pinouts Figure 1. Pin Diagram - 100-Pin TQFP Package (14 x 14 x 1.4 mm) Table 1.
PAGE 4
PRELIMINARY CY8CNP102B, CY8CNP102E Table 1.
PAGE 5
PRELIMINARY CY8CNP102B, CY8CNP102E Table 1. Pin Definitions - 100-Pin TQFP (continued) Pin Number Pin Name 79 HSB# 80 Vcc 81 - 85 NC 86 - 90 Vss 91 - 98 NC 99 NV_C 100 P0_7 Type Digital Pin Definition Analog Weak Pull up. Connect 10kΩ to Vcc. Power Supply Voltage Not connected on the die Power Ground Not connected on the die Connect to Pin 61 (NV_C to EN_C).Weak Pull up. Connect 10kΩ to Vcc.
PAGE 6
PRELIMINARY Programmable Digital System The digital system contains 16 digital PSoC blocks. Each block is an 8-bit resource that is used alone or combined with other blocks to form 8, 16, 24, and 32-bit peripherals, which are called user module references.
PAGE 7
PRELIMINARY CY8CNP102B, CY8CNP102E Development Tools PSoC Designer Software Subsystems PSoC Designer is a Microsoft® Windows based, integrated development environment for Programmable System-on-Chip (PSoC) devices. The PSoC Designer IDE and application run on Windows NT 4.0, Windows 2000, Windows Millennium (Me), Microsoft Vista, and Windows XP.
PAGE 8
PRELIMINARY Online Help System The online help system displays online, context sensitive help for the user. Designed for procedural and quick reference, each functional subsystem has its own context sensitive help. This system also provides tutorials and links to FAQs and an Online Support Forum to aid the designer in getting started. Hardware Tools In-Circuit Emulator A low cost, high functionality ICE (In-Circuit Emulator) is available for development support.
PAGE 9
PRELIMINARY The last step in the development process takes place inside the PSoC Designer’s Debugger subsystem. The Debugger downloads the HEX image to the In-Circuit Emulator (ICE) where it runs at full speed. The Debugger capabilities rival those of systems costing much more.
PAGE 10
PRELIMINARY CY8CNP102B, CY8CNP102E 3.3V Operation Absolute Maximum Ratings Table 3. 3.3V Absolute Maximum Ratings (CY8CNP102B) Symbol Description Min Typ Max Units o TSTG Storage Temperature -55 25 +100 C TA Ambient Temperature with Power Applied -40 – +85 oC Vcc Supply Voltage on Vcc Relative to Vss -0.5 – +4.1 V VIO DC Input Voltage Vss - 0.5 – Vcc + 0.5 V VIOZ DC Voltage Applied to Tri-state Vss - 0.5 – Vcc + 0.
PAGE 11
PRELIMINARY CY8CNP102B, CY8CNP102E DC Electrical Characteristics The following DC electrical specifications list the guaranteed maximum and minimum specifications for the voltage and temperature range: 3.0V to 3.6V over the Temperature range of -40°C ≤ TA ≤ 85°C. Typical parameters apply to 3.3V at 25°C and are for design guidance only. DC Chip Level Specifications Table 5. 3.3V DC Chip Level Specifications (CY8CNP102B) Symbol Description Min Typ Max Units Notes Vcc Supply Voltage 3.00 – 3.
PAGE 12
PRELIMINARY CY8CNP102B, CY8CNP102E DC Operational Amplifier Specifications The Operational Amplifier is a component of both the Analog Continuous Time PSoC blocks and the Analog Switched Capacitor PSoC blocks. The guaranteed specifications are measured in the Analog Continuous Time PSoC block. Table 7. 3.
PAGE 13
PRELIMINARY CY8CNP102B, CY8CNP102E DC Analog Output Buffer Specifications Table 9. 3.3V DC Analog Output Buffer Specifications (CY8CNP102B) Symbol Description VOSOB Input Offset Voltage (Absolute Value) TCVOSOB Average Input Offset Voltage Drift VCMOB Common-Mode Input Voltage Range ROUTOB Output Resistance VOHIGHOB VOLOWOB ISOB Typ Max Units – 3 12 mV – +6 – μV/°C 0.5 - Vcc - 1.0 V Power = Low – – 10 Ω Power = High – – 10 Ω Power = Low 0.5 x Vcc + 1.
PAGE 14
PRELIMINARY CY8CNP102B, CY8CNP102E DC Analog Reference Specifications The guaranteed specifications are measured through the Analog Continuous Time PSoC blocks. The power levels for AGND refer to the power of the Analog Continuous Time PSoC block. The power levels for RefHi and RefLo refer to the Analog Reference Control register. The limits stated for AGND include the offset error of the AGND buffer local to the Analog Continuous Time PSoC block. Reference control power is high. Table 10. 3.
PAGE 15
PRELIMINARY CY8CNP102B, CY8CNP102E DC POR, SMP, and LVD Specifications Table 12. 3.3V DC POR, SMP, and LVD Specifications (CY8CNP102B) Symbol Description Min Typ Max Units Vdd Value for PPOR Trip (positive ramp) VPPOR0R PORLEV[1:0] = 00b 2.91 V 2.82 V Vdd Value for PPOR Trip (negative ramp) VPPOR0 PORLEV[1:0] = 00b PPOR Hysteresis VPH0 PORLEV[1:0] = 00b 92 mV VPH1 PORLEV[1:0] = 01b 0 mV VPH2 PORLEV[1:0] = 10b 0 mV Vdd Value for LVD Trip VLVD0 VM[2:0] = 000b 2.86 2.92 2.
PAGE 16
PRELIMINARY CY8CNP102B, CY8CNP102E DC Programming Specifications Table 13. 3.3V DC Programming Specifications (CY8CNP102B) Symbol Description Min Typ Max Units – 10 30 mA Input Low Voltage During Programming or Verify – – 0.8 V Input High Voltage During Programming or Verify 2.2 – – V IILP Input Current when Applying Vilp to P1[0] or P1[1] During Programming or Verify – – 0.2 mA Driving internal pull down resistor.
PAGE 17
PRELIMINARY CY8CNP102B, CY8CNP102E AC Electrical Characteristics The following AC electrical specifications list the guaranteed maximum and minimum specifications for the voltage and temperature range: 3.0V to 3.6V over the temperature range of -40°C ≤ TA ≤ 85°C. Typical parameters apply to 3.3V at 25°C and are for design guidance only. AC Chip Level Specifications Table 14. 3.
PAGE 18
PRELIMINARY CY8CNP102B, CY8CNP102E In the following table, tHRECALL starts from the time Vcc rises above VSWITCH. If an SRAM WRITE has not taken place since the last nonvolatile cycle, no STORE occurs. Industrial grade devices require 15 ms maximum. Table 15.3.3V nvSRAM AutoStore/Power Up RECALL (CY8CNP102B) Parameter nvSRAM Description tHRECALL Power Up RECALL Duration tSTORE STORE Cycle Duration VSWITCH Low Voltage Trigger Level tVccRISE VCC Rise Time Min Unit Max 20 ms 12.5 ms 2.
PAGE 19
PRELIMINARY CY8CNP102B, CY8CNP102E AC Operational Amplifier Specifications Settling times, slew rates, and gain bandwidth are based on the Analog Continuous Time PSoC block. Table 17. 3.3V AC Operational Amplifier Specifications (CY8CNP102B) Symbol TROA TSOA SRROA SRFOA BWOA ENOA Description Min Typ Max Units Rising Settling Time to 0.1% of a 1V Step (10 pF load, Unity Gain) Power = Low, Opamp Bias = Low – – 3.92 μs Power = Medium, Opamp Bias = High – – 0.
PAGE 20
PRELIMINARY CY8CNP102B, CY8CNP102E Table 18. 3.3V AC Digital Block Specifications (CY8CNP102B) (continued) Function Description Min Typ Max Units CRCPRS Maximum Input Clock Frequency (PRS Mode) – – 24.6 MHz 3.0V ≤ Vcc ≤ 3.6V CRCPRS Maximum Input Clock Frequency (CRC Mode) – – 24.6 MHz 3.0V ≤ Vcc ≤ 3.6V. SPIM Maximum Input Clock Frequency – – 8.2 MHz Maximum data rate at 4.1 MHz due to 2 x over clocking. SPIS Maximum Input Clock Frequency – – 4.
PAGE 21
PRELIMINARY CY8CNP102B, CY8CNP102E AC Programming Specifications Table 20. 3.
PAGE 22
PRELIMINARY CY8CNP102B, CY8CNP102E 5V Operation Absolute Maximum Ratings Table 22. 5V Absolute Maximum Ratings (CY8CNP102E) Symbol Description Min Typ Max Units TSTG Storage Temperature -55 25 +100 o TA Ambient Temperature with Power Applied -40 – +85 o Vcc Supply Voltage on Vcc Relative to Vss -0.5 – +6.0 V VIO DC Input Voltage Vss - 0.5 – Vcc + 0.5 V VIOZ DC Voltage Applied to Tri-state Vss - 0.5 – Vcc + 0.
PAGE 23
PRELIMINARY CY8CNP102B, CY8CNP102E DC Electrical Characteristics The following DC electrical specifications lists the guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V over the Temperature range of -40°C ≤ TA ≤ 85°C. Typical parameters apply to 5V at 25°C and are for design guidance only. DC Chip Level Specifications Table 24. 5V DC Chip-Level Specifications (CY8CNP102E) Min Typ Max Units Vcc Symbol Supply Voltage Description 4.75 – 5.
PAGE 24
PRELIMINARY CY8CNP102B, CY8CNP102E DC Operational Amplifier Specifications The Operational Amplifier is a component of both the Analog Continuous Time PSoC blocks and the Analog Switched Capacitor PSoC blocks. The guaranteed specifications are measured in the Analog Continuous Time PSoC block. Table 26. 5V DC Operational Amplifier Specifications (CY8CNP102E) Symbol VOSOA Description Min Typ Max Units Power = Low, Opamp Bias = High – 1.6 10 mV Power = Medium, Opamp Bias = High – 1.
PAGE 25
PRELIMINARY CY8CNP102B, CY8CNP102E DC Analog Output Buffer Specifications Table 28. 5V DC Analog Output Buffer Specifications (CY8CNP102E) Symbol VOSOB Description Min Typ Max – 3 12 mV – +6 – μV/°C 0.5 – Vcc - 1.0 V Power = Low – – 1 Ω Power = High – – 1 Ω Power = Low 0.5 x Vcc + 1.3 – – V Power = High 0.5 x Vcc + 1.3 – – V Power = Low – – 0.5 x Vcc - 1.3 V Power = High – – 0.5 x Vcc - 1.3 V – 1.1 2 mA Power = High – 2.
PAGE 26
PRELIMINARY CY8CNP102B, CY8CNP102E DC Analog PSoC NV Block Specifications Table 30. 5V DC Analog PSoC NV Block Specifications (CY8CNP102E) Symbol Description Min Typ Max Units RCT Resistor Unit Value (Continuous Time) – 12.2 – kΩ CSC Capacitor Unit Value (Switch Cap) – 80 – fF Min Typ Max Units DC POR, SMP, and LVD Specifications Table 31. 5V DC POR, SMP, and LVD Specifications (CY8CNP102E) Symbol Description Vdd Value for PPOR Trip (positive ramp) VPPOR0R PORLEV[1:0] = 00b 2.
PAGE 27
PRELIMINARY CY8CNP102B, CY8CNP102E DC Programming Specifications Table 32. 5V DC Programming Specifications (CY8CNP102E) Symbol Description Min Typ Max Units – 10 30 mA Input Low Voltage During Programming or Verify – – 0.8 V Input High Voltage During Programming or Verify 2.2 – – V Input Current when Applying Vilp to P1[0] or P1[1] During Programming or Verify – – 0.2 mA Driving internal pull down resistor.
PAGE 28
PRELIMINARY CY8CNP102B, CY8CNP102E AC Electrical Characteristics The following AC electrical specifications lists the guaranteed maximum and minimum specifications for the voltage and temperature range: 4.75V to 5.25V over the Temperature range of -40°C ≤ TA ≤ 85°C. Typical parameters apply to 5V at 25°C and are for design guidance only. AC Chip Level Specifications Table 33.
PAGE 29
PRELIMINARY CY8CNP102B, CY8CNP102E In the following table, tHRECALL starts from the time Vcc rises above VSWITCH. If an SRAM WRITE has not taken place since the last nonvolatile cycle, no STORE takes place. Industrial grade devices require 15 ms maximum. Table 34. 5V nvSRAM AutoStore/Power Up RECALL (CY8CNP102E) Parameter nvSRAM Description tHRECALL Power Up RECALL Duration tSTORE STORE Cycle Duration VSWITCH Low Voltage Trigger Level tVccRISE VCC Rise Time Min Unit Max 20 ms 12.5 ms 4.
PAGE 30
PRELIMINARY CY8CNP102B, CY8CNP102E AC Operational Amplifier Specifications Settling times, slew rates, and gain bandwidth are based on the Analog Continuous Time PSoC block. Table 36. 5V AC Operational Amplifier Specifications (CY8CNP102E) Symbol TROA Description SRFOA – – 3.9 μs – – 0.72 μs – – 0.62 μs – – 5.9 μs Falling Settling Time to 0.1% for a 1V Step (10 pF load, Unity Gain) Power = Medium, Opamp Bias = High – – 0.92 μs Power = High, Opamp Bias = High – – 0.
PAGE 31
PRELIMINARY CY8CNP102B, CY8CNP102E Table 37. 5V AC Digital Block Specifications (CY8CNP102E) (continued) Function Description Min Typ Max Units Notes CRCPRS (CRC Mode) Maximum Input Clock Frequency – – 24.6 MHz 4.75V ≤ Vcc ≤ 5.25V. SPIM Maximum Input Clock Frequency – – 8.2 MHz Maximum data rate at 4.1 MHz due to 2 x over clocking. SPIS Maximum Input Clock Frequency – – 4.1 ns 50 – – ns – – 24.6 MHz Maximum data rate at 3.08 MHz due to 8 x over clocking. – – 49.
PAGE 32
PRELIMINARY CY8CNP102B, CY8CNP102E AC Programming Specifications Table 39.
PAGE 33
PRELIMINARY CY8CNP102B, CY8CNP102E Switching Waveforms Figure 8. AutoStore/Power Up RECALL No STORE occurs without atleast one SRAM write STORE occurs only if a SRAM write has happened VCC VSWITCH tVCCRISE AutoStore tSTORE tSTORE POWER-UP RECALL tHRECALL tHRECALL Read & Write Inhibited Figure 9. PLL Lock Timing Diagram PLL E n a b le TP LLS LE W 24 MHz FPLL PLL G a in 0 Figure 10.
PAGE 34
PRELIMINARY Switching Waveforms CY8CNP102B, CY8CNP102E (continued) Figure 11. External Crystal Oscillator Startup Timing Diagram 32K S e le c t 3 2 kHz TO S F32K2 Figure 12. 24 MHz Period Jitter (IMO) Timing Diagram J it t e r 2 4 M 1 F 24M Figure 13. 32 kHz Period Jitter (ECO) Timing Diagram J it t e r 3 2 k F 32K2 ~ ~ ~ ~ Figure 14.
PAGE 35
PRELIMINARY CY8CNP102B, CY8CNP102E Part Numbering Nomenclature C Y 8 C N P 1 0 2 B - A X Cypress I Temp: C = Commercial I = Industrial Microcontroller X = Pb free C = CMOS A = 100TQFP B = 3.
PAGE 36
PRELIMINARY CY8CNP102B, CY8CNP102E Packaging Information This section describes the packaging specifications for the PSoC NV device and the thermal impedances for TQFP package. Note Emulation tools may require a larger area on the target PCB than the chip’s footprint. For a detailed description of the emulation tool dimensions, refer to the document “PSoC Emulator Pod Dimensions” at http://www.cypress.com/design/MR10161. Package Diagrams Figure 15. 100-Pin TQFP - 14 x 14 x 1.
PAGE 37
PRELIMINARY CY8CNP102B, CY8CNP102E Document History Page Document Title: CY8CNP102B/CY8CNP102E Nonvolatile Programmable System-on-Chip (PSoC® NV) Document Number: 001-43991 REV. ECN Orig.
PAGE 38
PRELIMINARY CY8CNP102B, CY8CNP102E Sales, Solutions, and Legal Information Worldwide Sales and Design Support Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office closest to you, visit us at cypress.com/sales. Products PSoC Clocks & Buffers Wireless Memories Image Sensors PSoC Solutions psoc.cypress.com clocks.cypress.com General Low Power/Low Voltage psoc.cypress.com/solutions psoc.cypress.com/low-power wireless.