ConsuMoBL Dual-Port Static RAM Specification Sheet

CYDC256B16, CYDC128B16,
CYDC064B16, CYDC128B08,
CYDC064B08
Document #: 001-01638 Rev. *E Page 23 of 26
Interrupt Timing Diagrams
Notes:
55. t
HA
depends on which enable pin (CE
L
or R/W
L
) is deasserted first.
56. t
INS
or t
INR
depends on which enable pin (CE
L
or R/W
L
) is asserted last.
Switching Waveforms (continued)
WRITE 1FFF (OR 1/3FFF)
t
WC
Right Side Clears INT
R
:
t
HA
READ 1FFF
t
RC
t
INR
WRITE 1FFE (OR 1/3FFE)
t
WC
Right Side Sets INT
L
:
Left Side Sets INT
R
:
Left Side Clears INT
L
:
READ 1FFE
t
INR
t
RC
ADDRESS
R
CE
L
R/W
L
INT
L
OE
L
ADDRESS
R
R/W
R
CE
R
INT
L
ADDRESS
R
CE
R
R/W
R
INT
R
OE
R
ADDRESS
L
R/W
L
CE
L
INT
R
t
INS
t
HA
t
INS
(OR 1/3FFF)
OR 1/3FFE)
[55]
[56]
[56]
[56]
[55]
[56]
[+] Feedback