Transceiver with Reclocker Specification Sheet

CYV15G0404DXB
Document #: 38-02097 Rev. *B Page 35 of 44
C04 INSELB LVTTL IN F02 RXDC[7] LVTTL OUT L20 TXDB[6] LVTTL IN
C05 VCC POWER F03 TXDC[0] LVTTL IN M01 RXDC[4] LVTTL OUT
C06 ULCD LVTTL IN PU F04 RCLKEND LVTTL IN PD M02 RXDC[5] LVTTL OUT
M03 RCLKENC LVTTL IN PD U03 TXDD[2] LVTTL IN W03 LFID
LVTTL OUT
M04 TXERRC LVTTL OUT U04 TXCTD[1] LVTTL IN W04 RXCLKD– LVTTL OUT
M17 REFCLKB+ PECL IN U05 VCC POWER W05 VCC POWER
M18 REFCLKB– PECL IN U06 RXDD[2] LVTTL OUT W06 RXDD[4] LVTTL OUT
M19 TXERRB LVTTL OUT U07 RXDD[1] LVTTL OUT W07 RXSTD[1] LVTTL OUT
M20 TXCLKB LVTTL IN PD U08 GND GROUND W08 GND GROUND
N01 GND GROUND U09 TXCTA[1] LVTTL IN W09 ADDR [3] LVTTL IN PU
N02 GND GROUND U10 ADDR [0] LVTTL IN PU W10 ADDR [1] LVTTL IN PU
N03 GND GROUND U11 REFCLKD– PECL IN W11 RXCLKA+ LVTTL OUT
N04 GND GROUND U12 TXDA[1] LVTTL IN W12 TXERRA LVTTL OUT
N17 GND GROUND U13 GND GROUND W13 GND GROUND
N18 GND GROUND U14 TXDA[4] LVTTL IN W14 TXDA[2] LVTTL IN
N19 GND GROUND U15 TXCTA[0] LVTTL IN W15 TXDA[6] LVTTL IN
N20 GND GROUND U16 VCC POWER W16 VCC POWER
P01 RXDC[1] LVTTL OUT U17 RXDA[2] LVTTL OUT W17 LFIA LVTTL OUT
P02 RXDC[0] LVTTL OUT U18 TXCTB[0] LVTTL IN W18 REFCLKA+ PECL IN
P03 RXSTC[0] LVTTL OUT U19 RXSTA[2] LVTTL OUT W19 RXDA[4] LVTTL OUT
P04 RXSTC[1] LVTTL OUT U20 RXSTA[1] LVTTL OUT W20 RXDA[1] LVTTL OUT
P17 TXDB[5] LVTTL IN V01 TXDD[3] LVTTL IN Y01 TXDD[6] LVTTL IN
P18 TXDB[4] LVTTL IN V02 TXDD[4] LVTTL IN Y02 TXCLKD LVTTL IN PD
P19 TXDB[3] LVTTL IN V03 TXCTD[0] LVTTL IN Y03 RXDD[7] LVTTL OUT
P20 TXDB[2] LVTTL IN V04 RXDD[6] LVTTL OUT Y04 RXCLKD+ LVTTL OUT
R01 RXSTC[2] LVTTL OUT V05 VCC POWER Y05 VCC POWER
R02 TXCLKOC LVTTL OUT V06 RXDD[3] LVTTL OUT Y06 RXDD[5] LVTTL OUT
R03 RXCLKC+ LVTTL OUT V07 RXSTD[0] LVTTL OUT Y07 RXDD[0] LVTTL OUT
R04 RXCLKC– LVTTL OUT V08 GND GROUND Y08 GND GROUND
R17 TXDB[1] LVTTL IN V09 RXSTD[2] LVTTL OUT Y09 TXCLKOD LVTTL OUT
R18 TXDB[0] LVTTL IN V10 ADDR [2] LVTTL IN PU Y10 NC NO CONNECT
R19 TXCTB[1] LVTTL IN V11 REFCLKD+ PECL IN Y11 TXCLKA LVTTL IN PD
R20 TXDB[7] LVTTL IN V12 TXCLKOA LVTTL OUT Y12 RXCLKA– LVTTL OUT
T01 VCC POWER V13 GND GROUND Y13 GND GROUND
T02 VCC POWER V14 TXDA[3] LVTTL IN Y14 TXDA[0] LVTTL IN
T03 VCC POWER V15 TXDA[7] LVTTL IN Y15 TXDA[5] LVTTL IN
T04 VCC POWER V16 VCC POWER Y16 VCC POWER
T17 VCC POWER V17 RXDA[7] LVTTL OUT Y17 TXERRD LVTTL OUT
T18 VCC POWER V18 RXDA[3] LVTTL OUT Y18 REFCLKA– PECL IN
T19 VCC POWER V19 RXDA[0] LVTTL OUT Y19 RXDA[6] LVTTL OUT
T20 VCC POWER V20 RXSTA[0] LVTTL OUT Y20 RXDA[5] LVTTL OUT
U01 TXDD[0] LVTTL IN W01 TXDD[5] LVTTL IN
U02 TXDD[1] LVTTL IN W02 TXDD[7] LVTTL IN
Table 11. Package Coordinate Signal Allocation (continued)
Ball
ID
Signal Name Signal Type
Ball
ID
Signal Name Signal Type
Ball
ID
Signal Name Signal Type
[+] Feedback [+] Feedback