Low Speed USB Peripheral Controller Specification Sheet

ManualsBrandsCypress ManualsNetwork CardenCoRe CY7C63310

CY7C63310, CY7C638xx

Document 38-08035 Rev. *K Page 67 of 83

25. Voltage Vs CPU Frequency Characteristics

Figure 25-1. Voltage vs CPU Frequency Characteristics

Running the CPU at 24 MHz requires a minimum voltage of

4.75V. This applies to any CPU speed above 12 MHz, so using

an external clock between 12 - 24 MHz must also adhere to this

requirement. Operating the CPU at 24MHz when the supply

voltage is below 4.75V can cause undesired behavior and must

be avoided.

Many enCoRe II applications use USB Vbus 5V as the power

source for the device. According to the USB specification,

voltage can be less than 4.75V on Vbus (if the USB port is a low

power port the voltage can be between 4.4V and 5.25V). Even

for externally powered 5V applications, developers must

consider that on power up and power down voltage is less than

4.75V for some time. Firmware must be implemented properly to

prevent undesired behavior.

Use of 24 MHz requires the use of the high POR trip point of

approximately 4.55 - 4.65V (Register LVDCR 0x1E3,

PORLEV[1:0] = 10b). This setting is sufficient to protect the

device from problems due to operating at low voltage with CPU

speeds above 12 MHz. This must be set before setting the CPU

speed to greater than 12 MHz. For devices with slow power

ramps, changing the POR threshold to the high level may result

in one or more resets of the device as power ramps through the

chip default POR set point of approximately 2.6V up through the

high POR set point.

If multiple resets are undesirable for slow power ramps, then

firmware must do the following:

■

Set the Low Voltage Detection circuit (Register LVDCR 0x1E3,

VM[2:0]) for one of the set points above the POR (VM[2:0] =

110b ~4.73V or 111b ~4.82V).

■

Monitor the LVD until voltage is above the trip point (Register

VLTCMP 0x1E4, bit 1 is clear).

■

Debounce the indication to ensure that voltage is above the set

point for possible noisy supplies.

■

Set the POR to the high set point.

■

Shift CPU speed to 24 MHz.

If the supply voltage dips below 4.75V and the application can

tolerate running at a CPU speed of 12 MHz, then application

firmware may also implement the following to minimize the

chance of a reset event due to a voltage transient:

■

Set the LVD for one of the desired high setting (~4.73V or

~4.82V).

■

Enable the LVD interrupt.

■

In the LVD ISR, reduce CPU speed to 12 MHz and shift the

POR to a lower threshold.

■

Firmware can monitor for VLTCMP to clear within the normal

application main loop.

■

Debounce the indication to ensure voltage is above the set

point.

■

Shift the POR to the high set point.

■

Shift the CPU to 24 MHz.

93 KHz

12 MHz

24 MHz

CPU Frequency

Vdd (volts)

4.00

4.75

5.50

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