Specifications

CY7C67200
Document Number: 38-08014 Rev. *J Page 23 of 93
Register Description
The Host n Control register allows high-level USB transaction
control.
Preamble Enable (Bit 7)
The Preamble Enable bit enables or disables the transmission of
a preamble packet before all low-speed packets. This bit should
only be set when communicating with a low-speed device.
1: Enable Preamble packet
0: Disable Preamble packet
Sequence Select (Bit 6)
The Sequence Select bit sets the data toggle for the next packet.
This bit has no effect on receiving data packets; sequence
checking must be handled in firmware.
1: Send DATA1
0: Send DATA0
Sync Enable (Bit 5)
The Sync Enable bit synchronizes the transfer with the SOF
packet in full-speed mode and the EOP packet in low-speed
mode.
1: The next enabled packet will be transferred after the SOF or
EOP packet is transmitted
0: The next enabled packet will be transferred as soon as the SIE
is free
ISO Enable (Bit 4)
The ISO Enable bit enables or disables an Isochronous trans-
action.
1: Enable Isochronous transaction
0: Disable Isochronous transaction
Arm Enable (Bit 0)
The Arm Enable bit arms an endpoint and starts a transaction.
This bit is automatically cleared to ‘0’ when a transaction is
complete.
1: Arm endpoint and begin transaction
0: Endpoint disarmed
Reserved
All reserved bits must be written as ‘0’.
Host n Address Register [R/W]
■ Host 1 Address Register 0xC082
■ Host 2 Address Register 0xC0A2
Figure 19. Host n Address Register
Register Description
The Host n Address register is used as the base pointer into
memory space for the current host transactions.
Address (Bits [15:0])
The Address field sets the address pointer into internal RAM or
ROM.
Bit # 15 14 13 12 11 10 9 8
Field Address...
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
Default 0 0 0 0 0 0 0 0
Bit # 7 6 5 4 3 2 1 0
Field ...Address
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
Default 0 0 0 0 0 0 0 0