Specifications

CY7C67200
Document Number: 38-08014 Rev. *J Page 25 of 93
Stall Flag (Bit 7)
The Stall Flag bit indicates that the peripheral device replied with
a Stall in the last transaction.
1: Device returned Stall
0: Device did not return Stall
NAK Flag (Bit 6)
The NAK Flag bit indicates that the peripheral device replied with
a NAK in the last transaction.
1: Device returned NAK
0: Device did not return NAK
Length Exception Flag (Bit 5)
The Length Exception Flag bit indicates the received data in the
data stage of the last transaction does not equal the maximum
Host Count specified in the Host n Count register. A Length
Exception can either mean an overflow or underflow and the
Overflow and Underflow flags (bits 11 and 10, respectively)
should be checked to determine which event occurred.
1: An overflow or underflow condition occurred
0: An overflow or underflow condition did not occur
Sequence Status (Bit 3)
The Sequence Status bit indicates the state of the last received
data toggle from the device. Firmware is responsible for
monitoring and handling the sequence status. The Sequence bit
is only valid if the ACK bit is set to ‘1’. The Sequence bit is set to
‘0’ when an error is detected in the transaction and the Error bit
will be set.
1: DATA1
0: DATA0
Timeout Flag (Bit 2)
The Timeout Flag bit indicates if a timeout condition occurred for
the last transaction. A timeout condition can occur when a device
either takes too long to respond to a USB host request or takes
too long to respond with a handshake.
1: Timeout occurred
0: Timeout did not occur
Error Flag (Bit 1)
The Error Flag bit indicates a transaction failed for any reason
other than the following: Timeout, receiving a NAK, or receiving
a STALL. Overflow and Underflow are not considered errors and
do not affect this bit. CRC5 and CRC16 errors will result in an
Error flag along with receiving incorrect packet types.
1: Error detected
0: No error detected
ACK Flag (Bit 0)
The ACK Flag bit indicates two different conditions depending on
the transfer type. For non-Isochronous transfers, this bit repre-
sents a transaction ending by receiving or sending an ACK
packet. For Isochronous transfers, this bit represents a
successful transaction that will not be represented by an ACK
packet.
1: For non-Isochronous transfers, the transaction was ACKed.
For Isochronous transfers, the transaction was completed
successfully.
0: For non-Isochronous transfers, the transaction was not
ACKed. For Isochronous transfers, the transaction was not
completed successfully.
Host n PID Register [W]
■ Host 1 PID Register 0xC086
■ Host 2 PID Register 0xC0A6
Figure 22. Host n PID Register
Bit # 15 14 13 12 11 10 9 8
Field Reserved
Read/Write - - - - - - - -
Default 0 0 0 0 0 0 0 0
Bit # 7 6 5 4 3 2 1 0
Field PID Select Endpoint Select
Read/Write W W W W W W W W
Default 0 0 0 0 0 0 0 0