Specifications

CY7C67200
Document Number: 38-08014 Rev. *J Page 31 of 93
Device n Endpoint n Control Register [R/W]
■ Device n Endpoint 0 Control Register [Device 1: 0x0200 Device 2: 0x0280]
■ Device n Endpoint 1 Control Register [Device 1: 0x0210 Device 2: 0x0290]
■ Device n Endpoint 2 Control Register [Device 1: 0x0220 Device 2: 0x02A0]
■ Device n Endpoint 3 Control Register [Device 1: 0x0230 Device 2: 0x02B0]
■ Device n Endpoint 4 Control Register [Device 1: 0x0240 Device 2: 0x02C0]
■ Device n Endpoint 5 Control Register [Device 1: 0x0250 Device 2: 0x02D0]
■ Device n Endpoint 6 Control Register [Device 1: 0x0260 Device 2: 0x02E0]
■ Device n Endpoint 7 Control Register [Device 1: 0x0270 Device 2: 0x02F0]
Figure 30. Device n Endpoint n Control Register
Register Description
The Device n Endpoint n Control register provides control over a
single EP in device mode. There are a total of eight endpoints for
each of the two ports. All endpoints have the same definition for
their Device n Endpoint n Control register.
IN/OUT Ignore Enable (Bit 6)
The IN/OUT Ignore Enable bit forces endpoint 0 (EP0) to ignore
all IN and OUT requests. This bit must be set so that EP0 only
excepts Setup packets at the start of each transfer. This bit must
be cleared to except IN/OUT transactions. This bit only applies
to EP0.
1: Ignore IN/OUT requests
0: Do not ignore IN/OUT requests
Sequence Select (Bit 6)
The Sequence Select bit determines whether a DATA0 or a
DATA1 will be sent for the next data toggle. This bit has no effect
on receiving data packets, sequence checking must be handled
in firmware.
1: Send a DATA1
0: Send a DATA0
Stall Enable (Bit 5)
The Stall Enable bit sends a Stall in response to the next request
(unless it is a setup request, which are always ACKed). This is a
sticky bit and continues to respond with Stalls until cleared by
firmware.
1: Send Stall
Device n Endpoint n Count Register 0x02n4 R/W
Device n Endpoint n Status Register 0x02n6 R/W
Device n Endpoint n Count Result Register 0x02n8 R/W
Device n Interrupt Enable Register 0xC08C/0xC0AC R/W
Device n Address Register 0xC08E/0xC0AE R/W
Device n Status Register 0xC090/0xCB0 R/W
Device n Frame Number Register 0xC092/0xC0B2 R
Device n SOF/EOP Count Register 0xC094/0xC0B4 W
Table 27. USB Device Only Registers (continued)
Register Name
Address
(Device 1/Device 2)
R/W
Bit # 15 14 13 12 11 10 9 8
Field Reserved
Read/Write - - - - - - - -
Default X X X X X X X X
Bit # 7 6 5 4 3 2 1 0
Field
IN/OUT
Ignore
Enable
Sequence
Select
Stall
Enable
ISO
Enable
NAK
Interrupt
Enable
Direction
Select
Enable Arm
Enable
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
Default X X X X X X X X