Specifications

CY7C67200
Document Number: 38-08014 Rev. *J Page 61 of 93
Register Description
The SPI Status register is a read only register that provides
status for the SPI port.
FIFO Error Flag (Bit 7)
The FIFO Error Flag bit is a read only bit that indicates if a FIFO
error occurred. When this bit is set to ‘1’ and the Transmit Empty
bit of the SPI Control register is set to ‘1’, then a Tx FIFO
underflow has occurred. Similarly, when set with the Receive Full
bit of the SPI Control register, a Rx FIFO overflow has
occured.This bit automatically clear when the SPI FIFO Init
Enable bit of the SPI Control register is set.
1: Indicates FIFO error
0: Indicates no FIFO error
Receive Interrupt Flag (Bit 2)
The Receive Interrupt Flag is a read only bit that indicates if a
byte mode receive interrupt has triggered.
1: Indicates a byte mode receive interrupt has triggered
0: Indicates a byte mode receive interrupt has not triggered
Transmit Interrupt Flag (Bit 1)
The Transmit Interrupt Flag is a read only bit that indicates a byte
mode transmit interrupt has triggered.
1: Indicates a byte mode transmit interrupt has triggered
0: Indicates a byte mode transmit interrupt has not triggered
Transfer Interrupt Flag (Bit 0)
The Transfer Interrupt Flag is a read only bit that indicates a
block mode interrupt has triggered.
1: Indicates a block mode interrupt has triggered
0: Indicates a block mode interrupt has not triggered
SPI Interrupt Clear Register [0xC0D0] [W]
Figure 65. SPI Interrupt Clear Register
Register Description
The SPI Interrupt Clear register is a write-only register that allows
the SPI Transmit and SPI Transfer Interrupts to be cleared.
Transmit Interrupt Clear (Bit 1)
The Transmit Interrupt Clear bit is a write-only bit that clears the
byte mode transmit interrupt. This bit is self-clearing.
1: Clear the byte mode transmit interrupt
0: No function
Transfer Interrupt Clear (Bit 0)
The Transfer Interrupt Clear bit is a write-only bit that will clear
the block mode interrupt. This bit is self clearing.
1: Clear the block mode interrupt
0: No function
Reserved
All reserved bits must be written as ‘0’.
SPI CRC Control Register [0xC0D2] [R/W]
Figure 66. SPI CRC Control Register
Bit # 15 14 13 12 11 10 9 8
Field Reserved
Read/Write - - - - - - - -
Default 0 0 0 0 0 0 0 0
Bit # 7 6 5 4 3 2 1 0
Field
Reserved Transmit
Interrupt Clear
Transfer
Interrupt Clear
Read/Write - - - - - - W W
Default 0 0 0 0 0 0 0 0
Bit # 15 14 13 12 11 10 9 8
Field
CRC Mode CRC
Enable
CRC
Clear
Receive
CRC
One in
CRC
Zero in
CRC
Reserved...
Read/Write R/W R/W R/W R/W R/W R R -
Default 0 0 0 0 0 0 0 0
Bit # 7 6 5 4 3 2 1 0
Field ...Reserved
Read/Write - - - - - - - -
Default 0 0 0 0 0 0 0 0