Specifications

CY7C67200
Document Number: 38-08014 Rev. *J Page 84 of 93
Errata
This section describes the errata for the CY7C67200. Details include errata trigger conditions, scope of impact, available workaround,
and silicon revision applicability.
Contact your local Cypress Sales Representative if you have questions.
Part Numbers Affected
CY7C67200 Qualification Status
In Production
CY7C67200 Errata Summary
The following table defines the errata applicability to available CY7C67200 family devices. An “X” indicates that the errata pertains to
the selected device.
Note Errata items, in the table below, are hyperlinked. Click on any item entry to jump to its description.
Part Number Device Characteristics
CY7C67200 All Packages
Items CY7C67200
Silicon
Revision
Fix Status
<xref>1. HPI Write to SIE Registers X A No fix is currently planned for future silicon
versions. Use workaround.
<xref>2. IDE Register Read When GPIO24 Pin is Low X A No fix is currently planned for future silicon
versions. Use workaround.
<xref>3. UART Does Not Recognize Framing Errors X A No fix is currently planned for future silicon
versions. Use workaround.
<xref>4. UART Does Not Override GPIO Control Regis-
ter
X A No fix is currently planned for future silicon
versions. Use workaround.
<xref>5. VBUS Interrupt (VBUS Valid) Requires De-
bouncing
X A No fix is currently planned for future silicon
versions. Use workaround.
<xref>6. Coupled SIE Interrupt Enable Bits X A No fix is currently planned for future silicon
versions. Use workaround.
<xref>7. Un-Initialized SIExmsg Registers X A No fix is currently planned for future silicon
versions. Use workaround.
<xref>8. BIOS USB Peripheral Mode: Descriptor Length X A No fix is currently planned for future silicon
versions. Use workaround.
<xref>9. Peripheral Short Packet Issue X A Will be fixed in future silicon revision. Use
workaround.
<xref>10. Data Toggle Corruption Issue X A Will be fixed in future silicon revision. Use
workaround.