Specifications

CY7C67200
Document Number: 38-08014 Rev. *J Page 85 of 93
1. HPI Write to SIE Registers
■ Problem Definition
Writing to the SIE2 Control register via HPI can corrupt the SIE1 control register.
Writing to the SIE1 Control register via HPI can corrupt the SIE2 control register.
■ Parameters Affected
SIE control registers
■ Trigger Condition(S)
When an external processor accesses the SIE1 or SIE2 register at the same time the internal CY16 CPU is also accessing the
opposite SIE, the SIE accessed by the CY16 CPU will be corrupted.
For example, the external processor writes a value of 0x80 to the SIE2 register 0xC0B0 while the internal CY16 is doing a read/write
to the SIE1 register 0xC08C, the SIE1 register 0xC08C, will be corrupted with the value 0x80.
■ Scope of Impact
If the internal CPU and external CPU access the SIEs at the same time, contention will occur resulting in incorrect data in one of
the SIE registers.
■ Workaround
1. Use the LCP COMM_WRITE_CTRL_REG to handle the writing to SIE registers.
2. Use download code to handle SIE WRITE commands.
3. Avoid accessing SIE register from the external CPU. For example: Route all the SIE interrupts to the software mailbox
interrupt registers 0x144 and 0x148. This requires user to create download code.
■ Fix Status
Use workaround. No fix is currently planned for future silicon revisions. An implementation example is included in the Cypress
Windows CE driver.
2. IDE Register Read When GPIO24 Pin is Low
■ Problem Definition
Part does not service USB ISRs when GPIO24 pin (also labeled as HPI_INT and IORDY) is low and any IDE register is read.
■ Parameters Affected
USB ISRs do not get serviced.
■ Trigger Conditions
The IDE registers (0xC050 through 0xC06E) should not be read unless IDE is being used. Debuggers that read all memory
locations while single stepping can cause this situation to manifest itself.
■ Scope of Impact
If debugging and using this pin, your application will appear to hang.
■ Workaround
When running in stand-alone mode, avoid using the GPIO24 pin if possible.
■ Fix Status
Other workarounds being investigated. No fix is currently planned for future silicon revisions.