Specifications

CY7C67200
Document Number: 38-08014 Rev. *J Page 87 of 93
5. VBUS Interrupt (VBUS Valid) Requires Debouncing
■ Problem Definition
The VBUS interrupt in the Host/Device Status Registers [0xC090 and 0xC0B0] and OTG Control Register [0xC098] triggers multiple
times whenever VBUS is turned on. It should only trigger once when VBUS rises above 4.4 V and once when VBUS falls from
above 4.4 V to 0 V.
■ Parameters Affected
Electrical.
■ Trigger Conditions
VBUS turned on.
■ Scope of Impact
Host/Device Registers and OTG Control Register trigger multiple times.
■ Workaround
When reading the status of this interrupt, a software debounce should be implemented.
■ Fix Status
No fix is currently planned for future silicon versions.
6. Coupled SIE Interrupt Enable Bits
■ Problem Definition
Host/Device 1 SIE events will still trigger an interrupt when only the Host/Device 2 SIE Interrupt Enable is set and vise versa.
■ Parameters Affected
Host/Device SIE Interrupts.
■ Trigger Conditions
Setting only 1 Host/Device SIE Interrupt Enable.
■ Scope of Impact
The Host/Device global Interrupt Enable bits can not be used to disable each Host/Device SIE independently. These bits are found
in the Interrupt Enable Register (0xC00E).
■ Workaround
If an SIE Interrupt is desired, both Host/Device 1 and Host/Device 2 Interrupt Enable bits should be set in the global Interrupt Enable
Register (0xC00E). To properly mask an SIE Interrupt to a single SIE, the lower level Host/Device Interrupt Enable Registers
(0xC08C and 0xC0AC) must be used. For example, setting the Host/Device 2 IE Register to 0x0000 will prevent any Host/Device
2 events from generating a Host/Device Interrupt. To disable all SIE interrupts, both Host/Device Interrupt Enable bits in the Interrupt
Enable Register should be cleared.
■ Fix Status
No fix is currently planned for future silicon versions. Examples provided in the Development Kit Software.