CY7C67200 EZ-OTG™ Programmable USB On-The-Go Host/Peripheral Controller EZ-OTG Features ■ Single-chip programmable USB dual-role (Host/Peripheral) controller with two configurable Serial Interface Engines (SIEs) and two USB ports ■ Supports USB OTG protocol ■ On-chip 48-MHz 16-bit processor with dynamically switchable clock speed ■ Configurable IO block supports a variety of IO options or up to 25 bits of General Purpose IO (GPIO) ■ 4K × 16 internal mask ROM contains built-in BIOS that supports a
CY7C67200 Contents Introduction ....................................................................... 3 Processor Core Functional Overview ............................. 3 Processor .................................................................... 3 Clocking ....................................................................... 3 Memory ....................................................................... 3 Interrupts .....................................................................
CY7C67200 Introduction Memory EZ-OTG™ (CY7C67200) is Cypress Semiconductor’s first USB On-The-Go (OTG) host/peripheral controller. EZ-OTG is designed to easily interface to most high-performance CPUs to add USB host functionality. EZ-OTG has its own 16-bit RISC processor to act as a coprocessor or operate in standalone mode. EZ-OTG also has a programmable IO interface block allowing a wide range of interface options. EZ-OTG has a built-in 4K × 16 masked ROM and an 8K × 16 internal RAM.
CY7C67200 USB Interface OTG Interface EZ-OTG has two built-in Host/Peripheral SIEs that each have a single USB transceiver, meeting the USB 2.0 specification requirements for full and low speed (high speed is not supported). In Host mode, EZ-OTG supports two downstream ports; each supports control, interrupt, bulk, and isochronous transfers. In Peripheral mode, EZ-OTG supports one peripheral port with eight endpoints for each of the two SIEs.
CY7C67200 UART Features ■ Slave SPI signaling synchronization and filtering ■ Supports baud rates of 900 to 115.2K ■ Slave SPI clock rates up to 2 MHz ■ 8-N-1 ■ Maskable interrupts for block and byte transfer modes ■ Individual bit transfer for non-byte aligned serial communication in PIO mode ■ Programmable delay timing for the active/inactive master SPI clock ■ Auto or manual control for master mode slave select signal ■ Complete access to internal memory UART Pins Table 5.
CY7C67200 Table 9. HPI Interface Pins [1, 2] (continued) HSS Pins Pin Name Table 8. HSS Interface Pins Pin Name Pin Number Pin Number A0 F5 F6 CTS F6 D15 RTS E4 D14 E4 RX E5 D13 E5 TX E6 D12 E6 D11 D4 Host Port Interface (HPI) D10 D5 EZ-OTG has an HPI interface. The HPI interface provides DMA access to the EZ-OTG internal memory by an external host, plus a bidirectional mailbox register for supporting high-level communication protocols.
CY7C67200 Component details: Component details: ■ D1 and D2: Schottky diodes with a current rating greater than 60 mA. ■ L1: Inductor with inductance of 10 µH and a current rating of at least 250 mA ■ C1: Ceramic capacitor with a capacitance of 0.1 µF. ■ D1: Schottky diode with a current rating of at least 250 mA ■ C2: Capacitor value must be no more that 6.5 µF since that is the maximum capacitance allowed by the USB OTG specification for a dual-role device. The minimum value of C2 is 1 µF.
CY7C67200 Crystal Interface Boot Configuration Interface The recommended crystal circuit to be used with EZ-OTG is shown in Figure 4. If an oscillator is used instead of a crystal circuit, connect it to XTALIN and leave XTALOUT unconnected. For further information on the crystal requirements, see Table 39, “Crystal Requirements,” on page 69. EZ-OTG can boot into any one of four modes. The mode it boots into is determined by the TTL voltage level of GPIO[31:30] at the time nRESET is deasserted.
CY7C67200 Operational Modes Standalone Mode There are two modes of operation: Coprocessor and Standalone. In standalone mode, there is no external processor connected to EZ-OTG. Instead, EZ-OTG’s own internal 16-bit CPU is the main processor and firmware is typically downloaded from an EEPROM. Optionally, firmware may also be downloaded via USB. Refer to Table 14 for booting into standalone mode. Coprocessor Mode EZ-OTG can act as a coprocessor to an external host processor.
CY7C67200 Power Savings and Reset Description Upon wakeup, code begins executing within 200 ms, the time it takes the PLL to stabilize. The EZ-OTG modes and reset conditions are described in this section. Table 15. wakeup Sources[3, 4] Power Savings Mode Description Wakeup Source (if enabled) Event USB Resume D+/D– Signaling OTGVBUS Level Sleep mode is used for USB applications to support USB suspend and non USB applications as the main chip power down mode.
CY7C67200 the BIOS ROM, refer to the Programmers documentation and the BIOS documentation. Registers During development with the EZ-OTG toolset, the lower area of User's space (0x04A4 to 0x1000) should be left available to load the GDB stub. The GDB stub is required to allow the toolset debug access into EZ-OTG. Some registers have different functions for a read vs. a write access or USB host vs. USB device mode. Therefore, registers of this type have multiple definitions for the same address.
CY7C67200 CPU Flags Register [0xC000] [R] Figure 7. CPU Flags Register Bit # 15 14 13 12 11 10 9 8 Read/Write – – – – Default 0 0 – – – – 0 0 0 0 0 0 Bit # 7 6 5 4 3 2 1 0 Global Interrupt Enable Negative Flag Overflow Flag Carry Flag Zero Flag Field Reserved... ...Reserved Field Read/Write – – – R R R R R Default 0 0 0 X X X X X Register Description The CPU Flags register is a read only register that gives processor flags status.
CY7C67200 Bank Register [0xC002] [R/W] Figure 8. Bank Register Bit # 15 14 13 12 Field Read/Write 11 10 9 8 Address... R/W R/W R/W R/W R/W R/W R/W R/W Default 0 0 0 0 0 0 0 1 Bit # 7 6 5 4 3 2 1 0 Field Read/Write Default ...Address Reserved R/W R/W R/W – – – – – 0 0 0 X X X X X Register Description . Table 17. Bank Register Example The Bank register maps registers R0–R15 into RAM.
CY7C67200 CPU Speed Register [0xC008] [R/W] Figure 10. CPU Speed Register Bit # 15 14 13 12 Field 11 10 9 8 Reserved... Read/Write - - - - - - - - Default 0 0 0 0 0 0 0 0 Bit # 7 6 5 4 3 2 1 0 Field ...Reserved CPU Speed Read/Write - - - - R/W R/W R/W R/W Default 0 0 0 0 1 1 1 1 Register Description The CPU Speed register allows the processor to operate at a user selected speed.
CY7C67200 Power Control Register [0xC00A] [R/W] Figure 11.
CY7C67200 Setting this bit to ‘1’ immediately initiates HALT mode. While in HALT mode, only the CPU is stopped. The internal clock still runs and all peripherals still operate, including the USB engines. The power savings using HALT in most cases will be minimal, but in applications that are very CPU intensive the incremental savings may provide some benefit. The HALT state is exited when any enabled interrupt is triggered.
CY7C67200 UART Interrupt Enable (Bit 3) Timer 1 Interrupt Enable (Bit 1) The UART Interrupt Enable bit enables or disables the following UART hardware interrupts: UART TX and UART RX. 1: Enable UART interrupt The Timer 1 Interrupt Enable bit enables or disables the TImer1 Interrupt Enable. When this bit is reset, all pending Timer 1 interrupts are cleared.
CY7C67200 USB Diagnostic Register [0xC03C] [R/W] Figure 14. USB Diagnostic Register Bit # 15 14 13 12 Reserved Port 2A Diagnostic Enable Reserved Port 1A Diagnostic Enable Read/Write - R/W - R/W - Default 0 0 0 0 Field Bit # 11 10 9 8 - - - 0 0 0 0 2 1 0 Reserved... 7 6 5 4 3 ...
CY7C67200 Watchdog Timer Register [0xC00C] [R/W] Figure 15. Watchdog Timer Register Bit # 15 14 13 12 Field Read/Write 11 10 9 8 Reserved... R/W R/W R/W R/W R/W R/W R/W R/W Default 0 0 0 0 0 0 0 0 Bit # 7 5 4 6 ...
CY7C67200 Timer n Register [R/W] ■ Timer 0 Register 0xC010 ■ Timer 1 Register 0xC012 Figure 16. Timer n Register Bit # 15 14 13 12 Field 11 10 9 8 Count... Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Default 1 1 1 1 1 1 1 1 Bit # 7 6 5 4 3 2 1 0 Field ...Count Read/Write Default R/W R/W R/W R/W R/W R/W R/W R/W 1 1 1 1 1 1 1 1 Register Description The Timer n Register sets the Timer n count.
CY7C67200 Register Description The USB n Control register is used in both host and device mode. It monitors and controls the SIE and the data lines of the USB ports. This register can be accessed by the HPI interface. Port A D+ Status (Bit 13) Port A Force D± State (Bits [4:3]) The Port A D+ Status bit is a read-only bit that indicates the value of DATA+ on Port A. The Port A Force D± State field controls the forcing state of the D+ D– data lines for Port A.
CY7C67200 USB Host Only Registers There are twelve sets of dedicated registers to USB host only operation. Each set consists of two identical registers (unless otherwise noted); one for Host Port 1 and one for Host Port 2. These register sets are covered in this section and summarized in Table 25. Table 25.
CY7C67200 1: The next enabled packet will be transferred after the SOF or EOP packet is transmitted Register Description The Host n Control register allows high-level USB transaction control. 0: The next enabled packet will be transferred as soon as the SIE is free Preamble Enable (Bit 7) The Preamble Enable bit enables or disables the transmission of a preamble packet before all low-speed packets. This bit should only be set when communicating with a low-speed device.
CY7C67200 Host n Count Register [R/W] ■ Host 1 Count Register 0xC084 ■ Host 2 Count Register 0xC0A4 Figure 20. Host n Count Register Bit # 15 14 13 Field 12 11 10 9 Reserved 8 Count... Read/Write - - - - - - R/W R/W Default 0 0 0 0 0 0 0 0 Bit # 7 6 5 4 3 2 1 0 Field Read/Write Default ...
CY7C67200 Stall Flag (Bit 7) Timeout Flag (Bit 2) The Stall Flag bit indicates that the peripheral device replied with a Stall in the last transaction. The Timeout Flag bit indicates if a timeout condition occurred for the last transaction. A timeout condition can occur when a device either takes too long to respond to a USB host request or takes too long to respond with a handshake.
CY7C67200 Table 26. PID Select Definition (continued) Register Description The Host n PID register is a write-only register that provides the PID and Endpoint information to the USB SIE to be used in the next transaction. PID Select (Bits [7:4]) The PID Select field defined as in Table 26. ACK and NAK tokens are automatically sent based on settings in the Host n Control register and do not need to be written in this register. Table 26.
CY7C67200 Host n Device Address Register [W] ■ Host 1 Device Address Register 0xC088 ■ Host 2 Device Address Register 0xC0A8 Figure 24. Host n Device Address Register Bit # 15 14 13 12 Field 11 10 9 8 Reserved... Read/Write - - - - - - - - Default 0 0 0 0 0 0 0 0 Bit # 7 6 5 4 3 2 1 0 Field ...
CY7C67200 1: Enable SOF/EOP timer interrupt 1: Enable Connect Change interrupt 0: Disable SOF/EOP timer interrupt 0: Disable Connect Change interrupt Port A Wake Interrupt Enable (Bit 6) Done Interrupt Enable (Bit 0) The Port A Wake Interrupt Enable bit enables or disables the remote wakeup interrupt for Port A. 0: Disable remote wakeup interrupt for Port A The Done Interrupt Enable bit enables or disables the USB Transfer Done interrupt.
CY7C67200 Port A Wake Interrupt Flag (Bit 6) Port A SE0 Status (Bit 2) The Port A Wake Interrupt Flag bit indicates remote wakeup on Port A. The Port A SE0 Status bit indicates if Port A is in an SE0 state or not. Together with the Port A Connect change Interrupt Flag bit, it can be determined whether a device was inserted (non-SE0 condition) or removed (SE0 condition).
CY7C67200 Host n SOF/EOP Counter Register [R] ■ Host 1 SOF/EOP Counter Register 0xC094 ■ Host 2 SOF/EOP Counter Register 0xC0B4 Figure 28. Host n SOF/EOP Counter Register Bit # 15 Field 14 13 12 11 Reserved 10 9 8 Counter... Read/Write - - R R R R R R Default X X X X X X X X Bit # 7 6 5 4 3 2 1 0 Read/Write R R R R R R R R Default X X X X X X X X Field ...
CY7C67200 Table 27.
CY7C67200 is set incorrectly, the setup will be ACKed and the Set-up Status Flag will be set (refer to the setup bit of the Device n Endpoint n Status register for details). 0: Do not send Stall ISO Enable (Bit 4) The ISO Enable bit enables and disables an Isochronous transaction. This bit is only valid for EPs 1–7 and has no function for EP0.
CY7C67200 Register Description The Device n Endpoint n Address register is used as the base pointer into memory space for the current Endpoint transaction. There are a total of eight endpoints for each of the two ports. All endpoints have the same definition for their Device n Endpoint n Address register. Address (Bits [15:0]) The Address field sets the base address for the current transaction on a signal endpoint.
CY7C67200 Register Description The Device n Endpoint n Count register designates the maximum packet size that can be received from the host for OUT transfers for a single endpoint. This register also designates the packet size to be sent to the host in response to the next IN token for a single endpoint. The maximum packet length is 1023 bytes in ISO mode. There are a total of eight endpoints for each of the two ports. All endpoints have the same definition for their Device n Endpoint n Count register.
CY7C67200 IN Exception Flag (Bit 8) The IN Exception Flag bit indicates when the device received an IN packet when armed for an OUT. Enable bit settings as long as the Device n EP n Control register Enable bit is set. 1: Setup packet was received 1: Received IN when armed for OUT 0: Setup packet was not received 0: Received OUT when armed for OUT Sequence Flag (Bit 3) Stall Flag (Bit 7) The Sequence Flag bit indicates whether the last data toggle received was a DATA1 or a DATA0.
CY7C67200 Device n Endpoint n Count Result Register [R/W] ■ Device n Endpoint 0 Count Result Register [Device 1: 0x0208 Device 2: 0x0288] ■ Device n Endpoint 1 Count Result Register [Device 1: 0x0218 Device 2: 0x0298] ■ Device n Endpoint 2 Count Result Register [Device 1: 0x0228 Device 2: 0x02A8] ■ Device n Endpoint 3 Count Result Register [Device 1: 0x0238 Device 2: 0x02B8] ■ Device n Endpoint 4 Count Result Register [Device 1: 0x0248 Device 2: 0x02C8] ■ Device n Endpoint 5 Count Result Registe
CY7C67200 Device n Interrupt Enable Register [R/W] ■ Device 1 Interrupt Enable Register 0xC08C ■ Device 2 Interrupt Enable Register 0xC0AC Figure 35.
CY7C67200 EP5 Interrupt Enable (Bit 5) EP2 Interrupt Enable (Bit 2) The EP5 Interrupt Enable bit enables or disables an endpoint five (EP5) Transaction Done interrupt. An EPx Transaction Done interrupt triggers when any of the following responses or events occur in a transaction for the device’s given Endpoint: send/receive ACK, send STALL, Timeout occurs, IN Exception Error, or OUT Exception Error.
CY7C67200 Device n Address Register [W] ■ Device 1 Address Register 0xC08E ■ Device 2 Address Register 0xC0AE Figure 36. Device n Address Register Bit # 15 14 13 12 Read/Write - - - - - - - - Default 0 0 0 0 0 0 0 0 Bit # 7 6 5 4 3 2 1 0 Field ...Reserved Field 11 10 9 8 Reserved... Address Read/Write - W W W W W W W Default 0 0 0 0 0 0 0 0 Register Description The Device n Address register holds the device address assigned by the host.
CY7C67200 0: Interrupt did not trigger 0: Interrupt did not trigger Reset Interrupt Flag (Bit 8) EP3 Interrupt Flag (Bit 3) The Reset Interrupt Flag bit indicates if the USB Reset Detected interrupt has triggered. The EP3 Interrupt Flag bit indicates if the endpoint three (EP3) Transaction Done interrupt has triggered.
CY7C67200 Device n Frame Number Register [R] ■ Device 1 Frame Number Register 0xC092 ■ Device 2 Frame Number Register 0xC0B2 Figure 38. Device n Frame Number Register Bit # 15 Field SOF/EOP Timeout Flag 14 13 12 SOF/EOP Timeout Interrupt Counter 11 10 Reserved 9 8 Frame... Read/Write R R R R - R R R Default 0 0 0 0 0 0 0 0 Bit # 7 6 5 4 3 2 1 0 Field ...
CY7C67200 The Count field contains the current value of the SOF/EOP down counter. At power-up and reset, this value is set to 0x2EE0 and for expected 1-ms SOF/EOP intervals, this SOF/EOP count should be increased slightly. Register Description The Device n SOF/EOP Count register must be written with the time expected between receiving a SOF/EOPs. If the SOF/EOP counter expires before an SOF/EOP is received, an SOF/EOP Timeout Interrupt can be generated.
CY7C67200 D+ Pull-down Enable (Bit 7) 0: OTG VBus is less than 0.8 V The D+ Pull-down Enable bit enables or disables a pull-down resistor on the OTG D+ data line. ID Status (Bit 1) 1: OTG D+ dataline pull-down resistor enabled The ID Status bit is a read only bit that indicates the state of the OTG ID pin on Port A.
CY7C67200 Table 30. Mode Select Definition (continued) Register Description The GPIO Control register configures the GPIO pins for various interface options. It also controls the polarity of the GPIO interrupt on IRQ0 (GPIO24). 001 000 Reserved GPIO – General Purpose Input Output Write Protect Enable (Bit 15) HSS Enable (Bit 7) The Write Protect Enable bit enables or disables the GPIO write protect. When Write Protect is enabled, the GPIO Mode Select [15:8] bits are read-only until a chip reset.
CY7C67200 Register Description The GPIO 0 Output Data register controls the output data of the GPIO pins. The GPIO 0 Output Data register controls GPIO15 to GPIO0 while the GPIO 1 Output Data register controls GPIO31 to GPIO19. When read, this register reads back the last data written, not the data on pins configured as inputs (see Input Data Register). Writing a 1 to any bit will output a high voltage on the corresponding GPIO pin. Reserved All reserved bits must be written as ‘0’.
CY7C67200 Register Description The GPIO 0 Input Data register reads the input data of the GPIO pins. The GPIO 0 Input Data register reads from GPIO15 to GPIO0 while the GPIO 1 Input Data register reads from GPIO31 to GPIO19. Every bit represents the voltage of that GPIO pin. GPIO 1 Input Data Register [0xC026] [R] Figure 45.
CY7C67200 Register Description The GPIO 0 Direction register controls the direction of the GPIO data pins (input/output). The GPIO 0 Direction register controls GPIO15 to GPIO0 while the GPIO 1 Direction register controls GPIO31 to GPIO19. When any bit of this register is set to ‘1’, the corresponding GPIO data pin becomes an output. When any bit of this register is set to ‘0’, the corresponding GPIO data pin becomes an input. Reserved All reserved bits must be written as ‘0’.
CY7C67200 HSS Control Register [0xC070] [R/W] Figure 48.
CY7C67200 Transmit Ready (Bit 4) Receive Packet Ready Flag (Bit 1) The Transmit Ready bit is a read only bit that indicates if the HSS Transmit FIFO is ready for the CPU to load new data for transmission. The Receive Packet Ready Flag bit is a read only bit that indicates if the HSS receive FIFO is full with eight bytes.
CY7C67200 Register Description The HSS Baud Rate register sets the HSS Baud Rate. At reset, the default value is 0x0017 which sets the baud rate to 2.0 MHz. Baud (Bits [12:0]) The Baud field is the baud rate divisor minus one, in units of 1/48 MHz. Therefore the Baud Rate = 48 MHz/(Baud + 1). This puts a constraint on the Baud Value as follows: (24 – 1) < Baud > (5000 – 1) Reserved All reserved bits must bit written as ‘0’. HSS Transmit Gap Register [0xC074] [R/W] Figure 50.
CY7C67200 Register Description The HSS Data register contains data received on the HSS port (not for block receive mode) when read. This receive data is valid when the Receive Ready bit of the HSS Control register is set to ‘1’. Writing to this register initiates a single byte transfer of data. The Transmit Ready Flag in the HSS Control register must read ‘1’ before writing to this register (this avoids disrupting the previous/current transmission).
CY7C67200 Register Description The HSS Receive Counter register designates the block byte length for the next HSS receive transfer. This register must be loaded with the word count minus one to start the block receive transfer. As each byte is received this register value is decremented. When read, this register indicates the remaining length of the transfer. Counter (Bits [9:0]) The Counter field value is equal to the word count minus one giving a maximum value of 0x03FF (1023) or 2048 bytes.
CY7C67200 Register Description HPI Registers The HSS Transmit Counter register designates the block byte length for the next HSS transmit transfer. This register must be loaded with the word count minus one to start the block transmit transfer. As each byte is transmitted this register value is decremented. When read, this register indicates the remaining length of the transfer. There are five registers dedicated to HPI operation. In addition, there is an HPI status port which can be address over HPI.
CY7C67200 Register Description 0: Do not route signal to CPU The Interrupt Routing register allows the HPI port to take over some or all of the SIE interrupts that usually go to the on-chip CPU. This register is read-only by the CPU but is read/write by the HPI port. By setting the appropriate bit to ‘1’, the SIE interrupt is routed to the HPI port to become the HPI_INTR signal and also readable in the HPI Status register. The bits in this register select where the interrupts are routed.
CY7C67200 HPI Swap 0 Enable (Bit 0) Both HPI Swap bits (bits 8 and 0) must be set to identical values. When set to ‘00’, the most significant data byte goes to HPI_D[15:8] and the least significant byte goes to HPI_D[7:0]. This is the default setting. By setting to ‘11’, the most significant data byte goes to HPI_D[7:0] and the least significant byte goes to HPI_D[15:8]. SIEXmsg Register [W] • SIE1msg Register 0x0144 • SIE2msg Register 0x0148 Figure 58.
CY7C67200 HPI Status Port [] [HPI: R] Figure 60.
CY7C67200 Done2 Flag (Bit 3) 1: Interrupt triggered In host mode the Done2 Flag bit is a read-only bit that indicates if a host packet done interrupt occurs on Host 2. In device mode this read only bit indicates if any of the endpoint interrupts occurs on Device 2. Firmware needs to determine which endpoint interrupt occurred.
CY7C67200 Register Description The SPI Configuration register controls the SPI port. Fields apply to both master and slave mode unless otherwise noted. 3Wire Enable (Bit 15) Master Active Enable (Bit 7) The 3Wire Enable bit indicates if the MISO and MOSI data lines are tied together allowing only half duplex operation. The Master Active Enable bit is a read-only bit that indicates if the master state machine is active or idle. This field only applies to master mode.
CY7C67200 SPI Control Register [0xC0CA] [R/W] Figure 62.
CY7C67200 Receive Bit Length (Bits [2:0]) The Receive Bit Length field controls whether a full byte or partial byte will be received. If Receive Bit Length is ‘000’ then a full byte will be received. If Receive Bit Length is ‘001’ to ‘111’, then the value indicates the number of bits that will be received. SPI Interrupt Enable Register [0xC0CC] [R/W] Figure 63. SPI Interrupt Enable Register Bit # 15 14 13 12 Field 11 10 9 8 Reserved...
CY7C67200 The Receive Interrupt Flag is a read only bit that indicates if a byte mode receive interrupt has triggered. 1: Indicates a byte mode receive interrupt has triggered 0: Indicates a byte mode receive interrupt has not triggered Register Description The SPI Status register is a read only register that provides status for the SPI port. FIFO Error Flag (Bit 7) Transmit Interrupt Flag (Bit 1) The FIFO Error Flag bit is a read only bit that indicates if a FIFO error occurred.
CY7C67200 Register Description 1: Clear CRC with all ones The SPI CRC Control register provides control over the CRC source and polynomial value. 0: No Function CRC Mode (Bits [15:14) The Receive CRC bit determines whether the receive bit stream or the transmit bit stream is used for the CRC data input in full duplex mode. This bit is a don’t care in half-duplex mode. Receive CRC (Bit 11) The CRCMode field selects the CRC polynomial as defined in Table 35.
CY7C67200 SPI Data Register [0xC0D6] [R/W] Figure 68. SPI Data Register Bit # 15 14 13 12 Field 11 10 9 8 Reserved Read/Write - - - - - - - - Default X X X X X X X X Bit # 7 6 5 4 3 2 1 0 Field Read/Write Default Data R/W R/W R/W R/W R/W R/W R/W R/W X X X X X X X X Register Description The SPI Data register contains data received on the SPI port when read. Reading it empties the eight byte receive FIFO in PIO byte mode.
CY7C67200 SPI Transmit Count Register [0xC0DA] [R/W] Figure 70. SPI Transmit Count Register Bit # 15 14 Field 13 12 11 10 Reserved 9 8 Count... Read/Write - - - - - R/W R/W R/W Default 0 0 0 0 0 0 0 0 Bit # 7 6 5 4 3 2 1 0 R/W R/W R/W R/W R/W R/W R/W R/W 0 0 0 0 0 0 0 0 Field Read/Write Default ...Count Register Description The SPI Transmit Count register designates the block byte length for the SPI transmit DMA transfer.
CY7C67200 Register Description The SPI Receive Count register designates the block byte length for the SPI receive DMA transfer. Count (Bits [10:0]) The Count field sets the count for the SPI receive DMA transfer. Reserved All reserved bits must be written as ‘0’. UART Registers There are three registers dedicated to UART operation. Each of these registers is covered in this section and summarized in Table 36. Table 36.
CY7C67200 Reserved All reserved bits must be written as ‘0’. UART Status Register [0xC0E2] [R] Figure 74. UART Status Register Bit # 15 14 13 12 Field 11 10 9 8 Reserved... Read/Write - - - - - - - - Default 0 0 0 0 0 0 0 0 Bit # 7 6 5 Field 4 3 2 ...
CY7C67200 Pin Diagram The following describes the CY7C67200 48-pin FBGA. Figure 76.
CY7C67200 Table 38.
CY7C67200 Table 38. Pin Descriptions (continued) Pin A6 F1 E2 E1 C1 D1 D2 G1 B1 H2, D6, A4 G6, B6, A1, H1 Name Reserved BOOSTVCC VSWITCH BOOSTGND OTGVBUS CSWITCHA CSWITCHB AVCC AGND VCC GND Type – Power Analog Output Ground Analog IO Analog Analog Power Ground Power Ground Description Tie to Gnd for normal operation. Booster Power Input: 2.7 V to 3.
CY7C67200 DC Characteristics Table 40. DC Characteristics[6] Min. Typ. Max. Unit VCC, AVCC Parameter Supply Voltage Description Conditions 3.0 3.3 3.6 V BoosVCC Supply Voltage 2.7 – 3.6 V VIH Input HIGH Voltage 2.0 – 5.5 V VIL Input LOW Voltage II Input Leakage Current VOH VOL IOH IOL CIN Input Pin Capacitance – – 0.8 V 0< VIN < VCC –10.0 – +10.0 μA Output Voltage HIGH IOUT = 4 mA 2.4 – – V Output LOW Voltage IOUT = –4 mA – – 0.
CY7C67200 Table 41. DC Characteristics: Charge Pump (continued) Parameter Description Min. Typ. Max. Unit VA_SESS_VALID A-Device Session Valid Conditions 0.8 – 2.0 V VB_SESS_VALID B-Device Session Valid 0.8 – 4.0 V VA_SESS_END B-Device Session End 0.2 – 0.8 V E Efficiency When Loaded 75 – % RPD Data Line Pull Down 14.25 – 24.
CY7C67200 Clock Timing tCLK tLOW XTALIN tFALL tHIGH tRISE Clock Timing Parameter fCLK vXINH[10] tCLK tHIGH tLOW tRISE tFALL Duty Cycle Description Clock Frequency Clock Input High (XTALOUT left floating) Min. – 1.5 Typ. 12.0 3.0 Max. – 3.6 Unit MHz V Clock Period Clock High Time Clock Low Time Clock Rise Time Clock Fall Time 83.17 36 36 – – 45 83.33 – – – – – 83.5 44 44 5.0 5.0 55 ns ns ns ns ns % I2C EEPROM Timing 1. I2C EEPROM Bus Timing - Serial I/O tHIGH tLOW tR tF SCL tSU.
CY7C67200 Figure 77. HPI (Host Port Interface) Write Cycle Timing tCYC tASU tWP tAH ADDR [1:0] tCSH tCSSU nCS nWR nRD Dout [15:0] tDSU Parameter tWDH Description Min. Typical Max. Unit tASU Address Setup –1 – – ns tAH Address Hold –1 – – ns tCSSU Chip Select Setup –1 – – ns tCSH Chip Select Hold –1 – – ns tDSU Data Setup 6 – – ns tWDH Write Data Hold 2 – – ns tWP Write Pulse Width 2 – – T[11] tCYC Write Cycle Time 6 – – T[11] Note 11.
CY7C67200 HPI (Host Port Interface) Read Cycle Timing tCYC tASU tRP tAH ADDR [1:0] tCSH tCSSU nCS tRDH nWR nRD Din [15:0] tACC Parameter Description tRDH Min. Typ. Max.
CY7C67200 HSS BYTE Mode Transmit qt_clk CPU may start another BYTE transmit right after TxRdy goes high CPU_A[2:0] CPUHSS_cs CPU_wr BT BT TxRdy flag HSS_TxD start bit Byte transmit triggered by a CPU write to the HSS_TxData register bit 0 bit 1 bit 2 bit 3 bit 4 bit 5 bit 6 bit 7 start of last data bit to TxRdy high: 0 min, 4 T max. (T is qt_clk period) TxRdy low to start bit delay: 0 min, BT max when starting from IDEL.
CY7C67200 Hardware CTS/RTS Handshake tCTShold tCTShold tCTSsetup tCTSsetup HSS_RTS HSS_CTS HSS_TxD Start of transmission delayed until HSS_CTS goes high Start of transmission not delayed by HSS_CTS tCTSset-up: HSS_CTS setup time before HSS_RTS = 1.5T min. tCTShold: HSS_CTS hold time after START bit = 0 ns min. T = 1/48 MHz. When RTS/CTS hardware handshake is enabled, transmission can be held off by deasserting HSS_CTS at least 1.5T before HSS_RTS. Transmission resumes when HSS_CTS returns HIGH.
CY7C67200 Register Summary Table 42. Register Summary R/W R Address Register 0x0140 HPI Breakpoint Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Default High Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Default Low Address... 0000 0000 ...
CY7C67200 Table 42.
CY7C67200 Table 42.
CY7C67200 Table 42. Register Summary (continued) R/W R/W R/W Address Register 0xC0D6 0xC0D8 SPI Data Port t SPI Transmit Address Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Default High Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Default Low Reserved xxxx xxxx Data xxxx xxxx Address... 0000 0000 ...Address R/W R/W 0xC0DA 0xC0DC SPI Transmit Count SPI Receive Address 0000 0000 Reserved Count... 0000 0000 ...Count 0000 0000 Address... 0000 0000 ...
CY7C67200 Ordering Information Table 43.
CY7C67200 Package Diagram Figure 78. 48-ball (7.00 mm × 7.00 mm × 1.2 mm) FBGA BA48 51-85096 *I Document #: 38-08014 Rev.
CY7C67200 Acronyms Document Conventions Table 44. Acronyms Used in this Document Units of Measure Acronym Description Table 45.
CY7C67200 Document History Page Document Title: CY7C67200 EZ-OTG™ Programmable USB On-The-Go Host/Peripheral Controller Document Number: 38-08014 Revision ECN Orig.
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