Specifications

CY7C67200
Document #: 38-08014 Rev. *H Page 10 of 85
Power Savings and Reset Description
The EZ-OTG modes and reset conditions are described in this
section.
Power Savings Mode Description
EZ-OTG has one main power savings mode, Sleep. For detailed
information on Sleep mode; See section “Sleep”.
Sleep mode is used for USB applications to support USB
suspend and non USB applications as the main chip power down
mode.
In addition, EZ-OTG is capable of slowing down the CPU clock
speed through the CPU Speed register [0xC008] without
affecting other peripheral timing. Reducing the CPU clock speed
from 48 MHz to 24 MHz reduces the overall current draw by
around 8 mA while reducing it from 48 MHz to 3 MHz reduces
the overall current draw by approximately 15 mA.
Sleep
Sleep mode is the main chip power down mode and is also used
for USB suspend. Sleep mode is entered by setting the Sleep
Enable (bit 1) of the Power Control register [0xC00A]. During
Sleep mode (USB Suspend) the following events and states are
true:
■ GPIO pins maintain their configuration during sleep (in
suspend).
■ External Memory Address pins are driven low.
■ XTALOUT is turned off.
■ Internal PLL is turned off.
■ Firmware must disable the charge pump (OTG Control register
[0xC098]) causing OTGVBUS to drop below 0.2 V. Otherwise
OTGVBUS will only drop to V
CC
– (2 schottky diode drops).
■ Booster circuit is turned off.
■ USB transceivers is turned off.
■ CPU suspends until a programmable wakeup event.
External (Remote) Wakeup Source
There are several possible events available to wake EZ-OTG
from Sleep mode as shown in Tab le 15. These may also be used
as remote wakeup options for USB applications. See section
“Power Control Register [0xC00A] [R/W]” on page 15.
Upon wakeup, code begins executing within 200 ms, the time it
takes the PLL to stabilize.
Power-On Reset (POR) Description
The length of the power-on-reset event can be defined by (V
CC
ramp to valid) + (Crystal start up). A typical application might
utilize a 12-ms power-on-reset event = ~7 ms + ~5 ms, respec-
tively.
Reset Pin
The Reset pin is active low and requires a minimum pulse dura-
tion of sixteen 12-MHz clock cycles (1.3 ms). A reset event re-
stores all registers to their default POR settings. Code execution
then begins 200 ms later at 0xFF00 with an immediate jump to
0xE000, the start of BIOS.
Note It should be noted that for up to 3 ms after BIOS starts
executing, GPIO[24:19] and GPIO[15:8] will be driven as outputs
for a test mode. If these pins need to be used as inputs, a series
resistor is required (10 ohm to 48 ohm is recommended). Refer
to BIOS documentation for addition details.
USB Reset
A USB Reset affects registers 0xC090 and 0xC0B0, all other
registers remain unchanged.
Memory Map
Memory map information is presented in this section.
Mapping
The EZ-OTG has just over 24 KB of addressable memory
mapped from 0x0000 to 0xFFFF. This 24 KB contains both
program and data space and is byte addressable. Figure 6.
shows the various memory region address locations.
Internal Memory
Of the internal memory, 15 KB is allocated for user’s program
and data code. The lower memory space from 0x0000 to 0x04A2
is reserved for interrupt vectors, general purpose registers, USB
control registers, the stack, and other BIOS variables. The upper
internal memory space contains EZ-OTG control registers from
0xC000 to 0xC0FF and the BIOS ROM itself from 0xE000 to
0xFFFF. For more information on the reserved lower memory or
Table 15. wakeup Sources
[3, 4]
Wakeup Source (if enabled) Event
USB Resume D+/D– Signaling
OTGVBUS Level
OTGID Any Edge
HPI Read
HSS Read
SPI Read
IRQ0 (GPIO 24) Any Edge
Notes
3. Read data will be discarded (dummy data).
4. HPI_INT will assert on a USB Resume.registers