Specifications

CY7C67200
Document #: 38-08014 Rev. *H Page 11 of 85
the BIOS ROM, refer to the Programmers documentation and
the BIOS documentation.
During development with the EZ-OTG toolset, the lower area of
User's space (0x04A4 to 0x1000) should be left available to load
the GDB stub. The GDB stub is required to allow the toolset
debug access into EZ-OTG.
Figure 6. Memory Map
Registers
Some registers have different functions for a read vs. a write
access or USB host vs. USB device mode. Therefore, registers
of this type have multiple definitions for the same address.
The default register values listed in this data sheet may be
altered to some other value during BIOS initialization. Refer to
the BIOS documentation for Register initialization information.
Processor Control Registers
There are eight registers dedicated to general processor control.
Each of these registers is covered in this section and is summa-
rized in Table 16.
HW INTs
SW INTs
0x0000 - 0x00FF
Primary Registers
Swap Registers
USB Registers
HPI Int / Mailbox
Slave Setup Packet
BIOS
USER SPACE
~15K
Internal Memory
Control Registers
0x0100 - 0x011F
0x0120 - 0x013F
0x0140 - 0x0148
0x014A - 0x01FF
0x0200- 0x02FF
LCP Variables
0x0300- 0x030F
BIOS Stack0x0310- 0x03FF
USB Slave & OTG0x0400- 0x04A2
0x04A4- 0x3FFF
0xC000- 0xC0FF
0xE000- 0xFFFF
Table 16. Processor Control Registers
Register Name Address R/W
CPU Flags Register 0xC000 R
Register Bank Register 0xC002 R/W
Hardware Revision Register 0xC004 R
CPU Speed Register 0xC008 R/W
Power Control Register 0xC00A R/W
Interrupt Enable Register 0xC00E R/W
Breakpoint Register 0xC014 R/W
USB Diagnostic Register 0xC03C W