Specifications

CY7C67200
Document #: 38-08014 Rev. *H Page 27 of 85
Host n Device Address Register [W]
■ Host 1 Device Address Register 0xC088
■ Host 2 Device Address Register 0xC0A8
Figure 24. Host n Device Address Register
Register Description
The Host n Device Address register is a write-only register that
contains the USB Device Address that the host wishes to
communicate with.
Address (Bits [6:0])
The Address field contains the value of the USB address for the
next device that the host is going to communicate with. This
value must be written by firmware.
Reserved
All reserved bits must be written as ‘0’.
Host n Interrupt Enable Register [R/W]
■ Host 1 Interrupt Enable Register 0xC08C
■ Host 2 Interrupt Enable Register 0xC0AC
Figure 25. Host n Interrupt Enable Register
Register Description
The Host n Interrupt Enable register allows control over
host-related interrupts.
In this register a bit set to ‘1’ enables the corresponding interrupt
while ‘0’ disables the interrupt.
VBUS Interrupt Enable (Bit 15)
The VBUS Interrupt Enable bit enables or disables the OTG
VBUS interrupt. When enabled this interrupt triggers on both the
rising and falling edge of VBUS at the 4.4 V status (only
supported in Port 1A). This bit is only available for Host 1 and is
a reserved bit in Host 2.
1: Enable VBUS interrupt
0: Disable VBUS interrupt
ID Interrupt Enable (Bit 14)
The ID Interrupt Enable bit enables or disables the OTG ID
interrupt. When enabled this interrupt triggers on both the rising
and falling edge of the OTG ID pin (only supported in Port 1A).
This bit is only available for Host 1 and is a reserved bit in Host 2.
1: Enable ID interrupt
0: Disable ID interrupt
SOF/EOP Interrupt Enable (Bit 9)
The SOF/EOP Interrupt Enable bit enables or disables the
SOF/EOP timer interrupt.
Bit # 15 14 13 12 11 10 9 8
Field Reserved...
Read/Write - - - - - - - -
Default 0 0 0 0 0 0 0 0
Bit # 7 6 5 4 3 2 1 0
Field ...Reserved Address
Read/Write - W W W W W W W
Default 0 0 0 0 0 0 0 0
Bit # 15 14 13 12 11 10 9 8
Field
VBUS
Interrupt Enable
ID Interrupt
Enable
Reserved SOF/EOP
Interrupt Enable
Reserved
Read/Write R/W R/W - - - - R/W -
Default 0 0 0 0 0 0 0 0
Bit # 7 6 5 4 3 2 1 0
Field
Reserved Port A
Wake Interrupt Enable
Reserved Port A Connect
Change
Interrupt Enable
Reserved Done
Interrupt Enable
Read/Write - R/W - R/W - - - R/W
Default 0 0 0 0 0 0 0 0