Specifications

CY7C67200
Document #: 38-08014 Rev. *H Page 44 of 85
Register Description
The GPIO Control register configures the GPIO pins for various
interface options. It also controls the polarity of the GPIO
interrupt on IRQ0 (GPIO24).
Write Protect Enable (Bit 15)
The Write Protect Enable bit enables or disables the GPIO write
protect. When Write Protect is enabled, the GPIO Mode Select
[15:8] bits are read-only until a chip reset.
1: Enable Write Protect
0: Disable Write Protect
SAS Enable (Bit 11)
The SAS Enable bit, when in SPI mode, reroutes the SPI port
SPI_nSSI pin to GPIO[15] rather then GPIO[9].
1: Reroute SPI_nss to GPIO[15]
0: Leave SPI_nss on GPIO[9]
Mode Select (Bits [10:8])
The Mode Select field selects how GPIO[15:0] and GPIO[24:19]
are used as defined in Table 30.
HSS Enable (Bit 7)
The HSS Enable bit routes HSS to GPIO[15:12].
1: HSS is routed to GPIO
0: HSS is not routed to GPIOs. GPIO[15:12] are free for other
purposes.
SPI Enable (Bit 5)
The SPI Enable bit routes SPI to GPIO[11:8]. If the SAS Enable
bit is set, it overrides and routes the SPI_nSSI pin to GPIO15.
1: SPI is routed to GPIO[11:8]
0: SPI is not routed to GPIO[11:8]. GPIO[11:8] are free for other
purposes.
Interrupt 0 Polarity Select (Bit 1)
The Interrupt 0 Polarity Select bit selects the polarity for IRQ0.
1: Sets IRQ0 to rising edge
0: Sets IRQ0 to falling edge
Interrupt 0 Enable (Bit 0)
The Interrupt 0 Enable bit enables or disables IRQ0. The GPIO
bit on the interrupt Enable register must also be set in order for
this for this interrupt to be enabled.
1: Enable IRQ0
0: Disable IRQ0
Reserved
All reserved bits must be written as ‘0’.
GPIO 0 Output Data Register [0xC01E] [R/W]
Figure 42. GPIO 0 Output Data Register
Table 30. Mode Select Definition
Mode Select
[10:8]
GPIO Configuration
111 Reserved
110 SCAN – (HW) Scan diagnostic. For produc-
tion test only. Not for normal operation
101 HPI – Host Port Interface
100 Reserved
011 Reserved
010 Reserved
001 Reserved
000 GPIO – General Purpose Input Output
Table 30. Mode Select Definition (continued)
Bit # 15 14 13 12 11 10 9 8
Field GPIO15 GPIO14 GPIO13 GPIO12 GPIO11 GPIO10 GPIO9 GPIO8
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
Default 0 0 0 0 0 0 0 0
Bit # 7 6 5 4 3 2 1 0
Field GPIO7 GPIO6 GPIO5 GPIO4 GPIO3 GPIO2 GPIO1 GPIO0
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
Default 0 0 0 0 0 0 0 0