Specifications

CY7C67200
Document #: 38-08014 Rev. *H Page 51 of 85
Register Description
The HSS Data register contains data received on the HSS port (not for block receive mode) when read. This receive data is valid
when the Receive Ready bit of the HSS Control register is set to ‘1’. Writing to this register initiates a single byte transfer of data. The
Transmit Ready Flag in the HSS Control register must read ‘1’ before writing to this register (this avoids disrupting the previous/current
transmission).
Data (Bits [7:0])
The Data field contains the data received or to be transmitted on the HSS port.
Reserved
All reserved bits must be written as ‘0’.
HSS Receive Address Register [0xC078] [R/W]
Figure 52. HSS Receive Address Register
Register Description
The HSS Receive Address register is used as the base pointer address for the next HSS block receive transfer.
Address (Bits [15:0])
The Address field sets the base pointer address for the next HSS block receive transfer.
HSS Receive Counter Register [0xC07A] [R/W]
Figure 53. HSS Receive Counter Register
Bit # 15 14 13 12 11 10 9 8
Field Address...
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
Default 0 0 0 0 0 0 0 0
Bit # 7 6 5 4 3 2 1 0
Field ...Address
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
Default 0 0 0 0 0 0 0 0
Bit # 15 14 13 12 11 10 9 8
Field Reserved Counter...
Read/Write - - - - - - R/W R/W
Default 0 0 0 0 0 0 0 0
Bit # 7 6 5 4 3 2 1 0
Field ...Counter
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
Default 0 0 0 0 0 0 0 0