Specifications

CY7C67200
Document #: 38-08014 Rev. *H Page 53 of 85
Register Description
The HSS Transmit Counter register designates the block byte
length for the next HSS transmit transfer. This register must be
loaded with the word count minus one to start the block transmit
transfer. As each byte is transmitted this register value is decre-
mented. When read, this register indicates the remaining length
of the transfer.
Counter (Bits [9:0])
The Counter field value is equal to the word count minus one
giving a maximum value of 0x03FF (1023) or 2048 bytes. When
the transfer is complete this register returns 0x03FF until
reloaded.
Reserved
All reserved bits must be written as ‘0’.
HPI Registers
There are five registers dedicated to HPI operation. In addition,
there is an HPI status port which can be address over HPI. Each
of these registers is covered in this section and are summarized
in Table 32.
HPI Breakpoint Register [0x0140] [R]
Figure 56. HPI Breakpoint Register
Register Description
The HPI Breakpoint register is a special on-chip memory location, which the external processor can access using normal HPI memory
read/write cycles. This register is read-only by the CPU but is read/write by the HPI port. The contents of this register have the same
effect as the Breakpoint register [0xC014]. This special Breakpoint register is used by software debuggers which interface through
the HPI port instead of the serial port.
When the program counter matches the Breakpoint Address, the INT127 interrupt triggers. To clear this interrupt, a zero value must
be written to this register.
Address (Bits [15:0])
The Address field is a 16-bit field containing the breakpoint address.
Interrupt Routing Register [0x0142] [R]
Figure 57. Interrupt Routing Register
Table 32. HPI Registers
Register Name Address R/W
HPI Breakpoint Register 0x0140 R
Interrupt Routing Register 0x0142 R
SIE1msg Register 0x0144 W
SIE2msg Register 0x0148 W
HPI Mailbox Register 0xC0C6 R/W
Bit # 15 14 13 12 11 10 9 8
Field Address...
Read/Write R R R R R R R R
Default 0 0 0 0 0 0 0 0
Bit # 7 6 5 4 3 2 1 0
Field ...Address
Read/Write R R R R R R R R
Default 0 0 0 0 0 0 0 0
Bit # 15 14 13 12 11 10 9 8
Field
VBUS to HPI
Enable
ID to HPI
Enable
SOF/EOP2 to
HPI Enable
SOF/EOP2 to
CPU Enable
SOF/EOP1 to
HPI Enable
SOF/EOP1 to
CPU Enable
Reset2 to HPI
Enable
HPI Swap 1
Enable
Read/Write R R R R R R R R
Default 0 001010 0
Bit # 7 6 5 4 3 2 1 0
Field
Resume2 to
HPI Enable
Resume1 to
HPI Enable
Reserved Done2 to HPI
Enable
Done1 to HPI
Enable
Reset1 to HPI
Enable
HPI Swap 0
Enable
Read/Write - - - - - - - -
Default 0 0 0 0 0 0 0 0