Specifications

CY7C67200
Document #: 38-08014 Rev. *H Page 8 of 85
Crystal Interface
The recommended crystal circuit to be used with EZ-OTG is
shown in Figure 4. If an oscillator is used instead of a crystal
circuit, connect it to XTALIN and leave XTALOUT unconnected.
For further information on the crystal requirements, see Table 39,
“Crystal Requirements,” on page 69.
Crystal Pins
Boot Configuration Interface
EZ-OTG can boot into any one of four modes. The mode it boots
into is determined by the TTL voltage level of GPIO[31:30] at the
time nRESET is deasserted. Tabl e 14 shows the different boot
pin combinations possible. After a reset pin event occurs, the
BIOS bootup procedure executes for up to 3 ms. GPIO[31:30]
are sampled by the BIOS during bootup only. After bootup these
pins are available to the application as GPIOs.
GPIO[31:30] must be pulled high or low, as needed, using
resistors tied to V
CC
or GND with resistor values between 5K
ohm and 15K ohm. GPIO[31:30] must not be tied directly to V
CC
or GND. Note that in Standalone mode, the pull ups on those two
pins are used for the serial I2C EEPROM (if implemented). The
resistors used for these pull ups must conform to the serial
EEPROM manufacturer's requirements.
If any mode other then standalone is chosen, EZ-OTG will be in
coprocessor mode. The device will power up with the appropriate
communication interface enabled according to its boot pins and
wait idle until a coprocessor communicates with it. See the BIOS
documentation for greater detail on the boot process.
Figure 4. Crystal Interface
Table 13. Crystal Pins
Pin Name Pin Number
XTALIN G3
XTALOUT G2
Y1
C1 = 22 pF
C2 = 22 pF
CY7C67200
XTALIN
XTALOUT
12MHz
Parallel Resonant
Fundamental Mode
500uW
20-33pf ±5%
Table 14. Boot Configuration Interface
GPIO31
(Pin 39)
GPIO30
(Pin 40)
Boot Mode
0 0 Host Port Interface (HPI)
0 1 High Speed Serial (HSS)
1 0 Serial Peripheral Interface (SPI, slave
mode)
1 1 I2C EEPROM (Standalone Mode)