Low-Power USB 2.0 Hub Controller Family Specification Sheet

ManualsBrandsCypress ManualsComputer HardwareEZ-USB HX2LP

PRELIMINARY

EZ-USB HX2LP

™

Low-Power USB 2.0 Hub Controller Fam

ily

CY7C656x

Cypress Semiconductor Corporation • 3901 North First Street • San Jose, CA 95134 • 408-943-2600

Document #: 38-08037 Rev. *D Revised March 31, 2005

1.0 Features

• USB 2.0 hub controller

• Compliant with the USB 2.0 specification

• Windows



Hardware-quality lab (WHQL)-compliant

• Up to four downstream ports supported

• Supports bus-power and self powered modes

• Single-TT and Multi-TT modes supported

— Single-TT option for low-cost

— Multi-TT option for high performance

•2-Port

— Single TT option for bus power

• Fit/form/function compatible option with CY7C65640

(TetraHub)

• Multiple package options

— Space-saving 56 QFN

• Single power supply requirement

— Internal regulator for reduced cost

• Integrated upstream pull-up resistor

• Integrated pull-down resistors for all downstream ports

• Integrated upstream and downstream termination

resistors

• Integrated port status indicator controls

• 24-MHz external crystal (integrated PLL)

• Configurable with external SPI EEPROM

— Vendor ID, Product ID, Device ID (VID/PID/DID)

— Number of active ports

— Number of removable ports

— Maximum power setting for high-speed and full-

speed

— Hub controller power setting

—Power-on timer

— Overcurrent detection mode

— Overcurrent timer

— Enable/Disable overcurrent timer

— Overcurrent pin polarity

— indicator pin polarity

— Compound device

— Enable full-speed only

— Disable port indicators

— Gang power switching

— Enable single-TT mode only

— Self/bus powered compatibility

— Fully configurable string descriptors for multiple

language support

• In-system EEPROM programming

2.0 Introduction

EZ-USB HX2LP is Cypress’s next-generation family of high-

performance, low-power USB 2.0 hub controllers. HX2LP is an

ultra low-power single-chip USB 2.0 hub controller with

integrated upstream and downstream transceivers, a USB

Serial Interface Engine (SIE), USB Hub Control and Repeater

logic, and Transaction Translator (TT) logic. Cypress has also

integrated many of the external passive components, such as

pull-up and pull-down resistors, reducing the overall bill-of-

materials required to implement a hub design. The entire

HX2LP portfolio consists of:

1. CY7C65640B (TetraHub LP): 4-port/multiple transaction

translator

This device option is fit/form/function compatible with Cy-

press’s existing CY7C65640 device. Cypress’s “Tetra” ar-

chitecture provides four downstream USB ports, each with

a dedicated Transaction Translator (TT), making it the high-

est-performance hub available. The TetraHub LP also of-

fers best-in-class power consumption. The CY7C65640B is

available in a 56 QFN (TetraHub pin-compatible) for space

saving designs.

2. CY7C65630: 4-port/single transaction translator

This device option is for ultra low-cost applications where

performance is secondary consideration. All four ports

must share a single transaction translator in this configura-

tion. The CY7C65630 is available in a 56 QFN and is also

pin for pin-compatible with the CY7C65640.

3. CY7C65620:

This device option is for a 2-port bus powered application.

Both ports must share a single transaction translator in this

configuration. The CY7C65620 is available in a 56 QFN

and is also pin for pin compatible with the CY7C65640.

All device options are supported by Cypress’s world-class

reference design kits, which include board schematics, bill of

materials, Gerber files, Orcad files, and thorough design

documentation.

Summary of content (23 pages)

PAGE 1
CY7C656xx PRELIMINARY EZ-USB HX2LP™ Low-Power USB 2.0 Hub Controller Family 1.0 Features 2.0 • USB 2.0 hub controller • Compliant with the USB 2.0 specification • Windows Hardware-quality lab (WHQL)-compliant • Up to four downstream ports supported • Supports bus-power and self powered modes • Single-TT and Multi-TT modes supported — Single-TT option for low-cost — Multi-TT option for high performance Introduction EZ-USB HX2LP is Cypress’s next-generation family of highperformance, low-power USB 2.
PAGE 2
CY7C656xx PRELIMINARY 3.0 Block Diagrams D+ D- U SB 2.0 PH Y 24 M Hz Cry s tal High-Speed USB C ontrol Logic Serial Interface Engine PLL SPI Com m unication Block U SB Upstream Port S P I_S CK S P I_S D S P I_CS Transaction T ranslator (X4) H ub Repeater TT RA M Routi ng Logi c U SB Downstream Port 1 US B 2.0 P HY D+ P ort P ower P ort Control S tatus D- P W R#[1] LE D OV R#[1] USB D ownstream Port 2 US B 2.
PAGE 3
CY7C656xx PRELIMINARY 3.0 Block Diagrams (continued) D+ D- U SB 2.0 PHY 24 M Hz Cry s tal H igh-Speed USB Contr ol Logic Serial Interface Engine PLL SPI C om m unication Block USB Upstream Port S P I_S CK S P I_S D S P I_CS Transaction Translator (X1) H ub Repeater TT RA M Routing Logic USB Dow nstream Port 1 US B 2.0 P HY D+ P ort P ower P ort Control S tatus D- P W R#[1] LE D OV R#[1] USB Downstream Port 2 US B 2.
PAGE 4
CY7C656xx PRELIMINARY 3.1 USB Serial Interface Engine (SIE) The SIE allows the CY7C656xx to communicate with the USB host through the USB repeater component of the HUB. The SIE handles the following USB activity independently of the HUB Control Block: • Bit stuffing/unstuffing • Checksum generation/checking • ACK/NAK/STALL • TOKEN type identification • Address checking. 3.
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CY7C656xx PRELIMINARY unpowered state. Once the hubs are configured, the ports are not driven, and the host may power the ports by sending a SetPortPower command to each port. After a port is powered, any connect or disconnect event is detected by the hub. Any change in the port state is reported by the hubs back to the host through the Status Change Endpoint (endpoint 1).
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CY7C656xx PRELIMINARY The LED control lines can also be modulated with a square wave for power conservation in systems using batteries. Alone with this there is also a polarity control for these pins, see section 9.3. In manual mode, the indicators are under the control of the host, which can turn on one of the LEDs, or leave them off. This is done by a system software USB Hub class request. Blinking of the LEDs is supported in Manual Mode.
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CY7C656xx PRELIMINARY DD–[4]/NC DD+[4]/NC VCC SPI_SCK 50 49 48 47 46 45 GREEN#[4]/NC SPI_SD 51 AMBER#[4]/NC GND 52 SELFPWR OVR#[4]/NC 53 RESET PWR#[4]/NC 54 GND OVR#[3]/NC 55 PWR#[3]/NC 56 VCC Pin Configuration GND 6.
PAGE 8
CY7C656xx PRELIMINARY 7.0 Pin Description Table Table 7-1 below displays the pin assignments. Table 7-1. Pin Assignments [3] CY7C65640B / CY7C65620 CY7C65630 Pin Pin 3 Name 3 VCC Type Default Description Power N/A VCC. This signal provides power to the chip. 7 7 VCC Power N/A VCC. This signal provides power to the chip. 11 11 VCC Power N/A VCC. This signal provides power to the chip. 15 15 VCC Power N/A VCC. This signal provides power to the chip. 19 19 VCC Power N/A VCC.
PAGE 9
CY7C656xx PRELIMINARY Table 7-1. Pin Assignments (continued)[3] CY7C65640B / CY7C65620 CY7C65630 Pin Pin Name Type Default Description Upstream Port 17 17 D– I/O/Z Z Upstream D– Signal. 18 18 D+ I/O/Z Z Upstream D+ Signal. 13 13 DD–[1] I/O/Z Z Downstream D– Signal. 14 14 DD+[1] I/O/Z Z Downstream D+ Signal. 36 36 AMBER#[1] O 1 LED. Driver output for Amber LED. Port Indicator Support. Default is Active LOW. Polarity is controlled through EEPROM.
PAGE 10
CY7C656xx PRELIMINARY 8.0 Default Descriptors 8.1 Device Descriptor The standard device descriptor for CY7C656xx is based on the VID, PID, and DID found in the SPI EEPROM. This VID/PID/DID in the EEPROM will overwrite the default VID/PID/DID. If no EEPROM is used, the CY7C656xx will enumerate with the default descriptor values as shown below.
PAGE 11
CY7C656xx PRELIMINARY 8.4 Endpoint Descriptor Byte Full Speed High Speed Field Name Description 0 0x07 0x07 bLength 7 Bytes 1 0x05 0x05 bDescriptorType ENDPOINT_DESCRIPTOR 2 0x81 0x81 bEndpointAddress IN Endpoint #1 3 0x03 0x03 bmAttributes Interrupt 4,5 0x0001 0x0001 wMaxPacketSize Maximum Packet Size 6 0xFF 0x0C bInterval Polling Rate Interface Descriptor[9,10] 8.
PAGE 12
CY7C656xx PRELIMINARY 8.8 Hub Descriptor Byte All Speed 0 0x09 1 0x29 2 0x04 [11] 0x02 3,4 0x0089[11] Field Name Description bLength 9 Bytes bDescriptorType HUB Descriptor bNbrPorts Number of ports supported, CY7C65640B or CY7C65630. Number of ports supported, CY7C65620.
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CY7C656xx PRELIMINARY 9.
PAGE 14
PRELIMINARY Byte Value (MSB->LSB) 7 EnableOverCurrentTimer[3:0], DisableOvercurrentTimer[3:0] 8 MaxPower (Full-speed) 9 MaxPower (High-speed) 10 Reserved 11 Reserved 12 HubControllerPower Full-Speed 13 HubControllerPower High-Speed 14 Reserved 15 Reserved 16 PowerOnTimer 17 IllegalHubDescriptor, CompoundDevice, FullspeedOnly, NoPortIndicators, Reserved, GangPowered, SingleTTOnly, Reserved 18 AmberPolarity, GreenPolarity, ModulateIndicators, PowerControlPolarity, OverCurrentPolarity,
PAGE 15
CY7C656xx PRELIMINARY tems that do not accept this, the IllegalHubDescriptor configuration bit may be set to allow CY7C656xx to accept a DescriptorType of 0x00 for this command. Default is 0, recommended setting is 1. Bit 0: OverCurrentMode2—Reported as bit 3 of the wHubCharacteristics field of the hub descriptor. If Bit 1 of this byte is set to ‘0’, over-current detection is enabled. If this bit (Bit 0) is set to ‘1’, the hub reports over-current on a per-port basis.
PAGE 16
CY7C656xx PRELIMINARY Byte c: iSerialNumber Byte 22: ActivePorts[3:0] Bits 3–0 are the ActivePorts[3:0] bits that indicates if the corresponding port is usable. For example, a two-port hub that uses ports 1 and 4 would set this field to 0x09. The total number of ports reported in the Hub Descriptor: bNbrPorts field is calculated from this. Array of addresses for the iSerialNumber strings. Each address is two bytes long, stored LSB first. The array has NumLangs entries (2 * NumLangs bytes).
PAGE 17
CY7C656xx PRELIMINARY Table 10-1.
PAGE 18
CY7C656xx PRELIMINARY Table 10-2.
PAGE 19
CY7C656xx PRELIMINARY 11.0 Upstream USB Connection The following is a schematic of the USB upstream connector. BUSPOWER VCC D– D– D+ D+ 2.2 µF 10V 100 kΩ GND SHELL 4.7 nF 250V 1 MΩ Figure 11-1. USB Upstream Port Connection 12.0 Downstream USB Connections The following is a schematic of the USB downstream connector. PWRx 150 µF 10V VCC 0.01 µF DD–[X] D– DD+[X] D+ GND SHELL Figure 12-1. USB Downstream Port Connection 13.
PAGE 20
CY7C656xx PRELIMINARY 14.0 System Block Diagram 5V BUSPOWER VCC D– D– D+ D+ PWR1 PWR1 2.2 µF 10V PWR4 OVR1 100 kΩ GND Power PWR2 Management PWR3 OVR2 PWR3 PWR2 OVR3 PWR4 OVR4 SHELL 4.7 nF 250V 150 µF 10V DD–[1] DD+[1] 0.01 µF VCC D– D+ GND SHELL PWR1 3.3V GREEN#[1] 680Ω 1 MΩ AMBER#[1] 680Ω SPI_SD SPI_SCK SPI EEPROM PWR2 SPI_SD 150 µF 10V SPI_CS DD–[2] DD+[2] 0.01 µF VCC D– D+ GND SHELL 24 MHz 3.
PAGE 21
CY7C656xx PRELIMINARY 15.0 Electrical Characteristics 15.1 Absolute Maximum Ratings 15.2 Operating Conditions Storage Temperature ................................ –65°C to +150 °C TA (Ambient Temperature Under Bias) ............. 0°C to +70°C Ambient Temperature with Power Applied ........ 0°C to +70°C Supply Voltage ...........................................+3.15V to +3.45V Supply Voltage to Ground Potential .............. –0.5V to +4.0V Ground Voltage .........................................
PAGE 22
CY7C656xx PRELIMINARY 16.0 Ordering Information Ordering Code Package Type CY7C65640B-56LFXC 56-pin QFN Mult-TT CY7C65630-56LFXC 56-pin QFN Single-TT CY7C65620-56LFXC 56-pin QFN 2-Port Single-TT CY46XX CY7C656xx USB 2.0 4 port Hub Reference Design Kit 17.0 Package Diagrams The CY7C656xx is available in a space-saving 56-pin QFN (8 × 8 mm). 56-Lead QFN 8 x 8 MM LF56A TOP VIEW BOTTOM VIEW SIDE VIEW 0.08[0.003] A C 1.00[0.039] MAX. 7.90[0.311] 8.10[0.319] 0.05[0.002] MAX. 0.80[0.031] MAX.
PAGE 23
CY7C656xx PRELIMINARY Document History Page Document Title: CY7C656xx EZ-USB HX2LP™ Low-Power USB 2.0 Hub Controller Family Document Number: 38-08037 REV. ECN NO. Issue Date Orig.