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The EZ-USB

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Integrated Circuit

Technical Reference

Summary of content (334 pages)

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The EZ-USBTM Integrated Circuit Technical Reference
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The information in this document is subject to change without notice and should not be construed as a commitment by Cypress Semiconductor Corporation. While reasonable precautions have been taken, Cypress Semiconductor Corporation assumes no responsibility for any errors that may appear in this document. No part of this document may be copied or reproduced in any form or by any means without the prior written consent of Cypress Semiconductor Corporation.
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Development Kit — Getting Started Documentation for the EZ-USB™ Xcelerator™ Development it. Includes an overview of the kit, descriptions of kit components with installation instructions, and details about the development board. Technical Reference Documentation of the EZ-USB controller. Includes details about the CPU, memory, input/output, ReNumeration™, bulk transfers, endpoint zero, isochronous transfers, interrupts, resets, power management, registers, AC/ DC parameters, and packages.
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EZ-USB Technical Reference Manual Table of Contents Table of Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . i Figures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . vii Tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . xi 1 Introducing EZ-USB ...............................................................
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1.16 1.17 1.18 1.19 1.20 2 EZ-USB CPU .................................................................................. 2-1 2.1 2.2 2.3 2.4 2.5 2.6 2.7 2.8 2.9 2.10 2.11 3 Introduction ............................................................................................. 3-1 8051 Memory .......................................................................................... 3-2 Expanding EZ-USB Memory ................................................................. 3-4 CS# and OE# Signals ...
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4.8 4.9 4.10 5 EZ-USB Enumeration and ReNumeration ..................................5-1 5.1 5.2 5.3 5.4 5.5 5.6 5.7 5.8 5.9 5.10 5.11 6 Introduction ............................................................................................. 5-1 The Default USB Device ........................................................................ 5-2 EZ-USB Core Response to EP0 Device Requests .................................. 5-4 Firmware Load ...............................................................
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.3.1 7.3.2 7.3.3 7.3.4 Get Status ................................................................................. 7-7 Set Feature ............................................................................. 7-10 Clear Feature ......................................................................... 7-12 Get Descriptor ....................................................................... 7-12 7.3.4.1 7.3.4.2 7.3.4.3 7.3.5 7.3.6 7.3.7 7.3.8 7.3.9 7.3.10 7.3.11 7.3.12 8 8.2 8.3 8.4 8.5 8.6 8.7 8.
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9.2 9.3 9.4 9.5 9.6 9.7 9.8 9.9 9.10 9.11 9.12 9.13 9.14 10 EZ-USB Resets ..............................................................................10-1 10.1 10.2 10.3 10.4 10.5 10.6 10.7 11 Introduction ........................................................................................... 10-1 EZ-USB Power-On Reset (POR) .......................................................... 10-1 Releasing the 8051 Reset ...................................................................... 10-3 10.3.
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12.8 12.9 12.10 12.11 12.12 12.13 12.14 12.15 12.16 12.17 13 EZ-USB AC/DC Parameters ....................................................... 13-1 13.1 14 13.0.1 Absolute Maximum Ratings ................................................... 13-1 13.0.2 Operating Conditions ............................................................ 13-1 13.0.3 DC Characteristics ................................................................ 13-1 Electrical Characteristics ...............................................
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Figures Figure 1-1. Figure 1-2. Figure 1-3. Figure 1-4. Figure 1-5. Figure 1-6. Figure 1-7. Figure 1-8. Figure 1-9. Figure 1-10. Figure 1-11. Figure 1-12. Figure 1-13. Figure 2-1. Figure 3-1. Figure 3-2. Figure 3-3. Figure 3-4. Figure 3-5. Figure 3-6. Figure 3-7. Figure 4-1. Figure 4-2. Figure 4-3. Figure 4-4. Figure 4-5. Figure 4-6. Figure 4-7. Figure 5-1. Figure 5-2. Figure 5-3. Figure 6-1. Figure 6-2. Figure 6-3. Figure 6-4. Figure 6-5. Figure 6-6. Figure 6-7. Figure 6-8. EZ-USB TRM v1.
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Figure 6-9. Figure 6-10. Figure 6-11. Figure 6-12. Figure 6-13. Figure 6-14. Figure 7-1. Figure 7-2. Figure 7-3. Figure 7-4. Figure 7-5. Figure 8-1. Figure 8-2. Figure 8-3. Figure 8-4. Figure 8-5. Figure 8-6. Figure 8-7. Figure 8-8. Figure 8-9. Figure 8-10. Figure 8-11. Figure 8-12. Figure 8-13. Figure 8-14. Figure 8-15. Figure 9-1. Figure 9-2. Figure 9-3. Figure 9-4. Figure 9-5. Figure 9-6. Figure 9-7. Figure 9-8. Figure 9-9. Figure 9-10. Figure 9-11. Figure 9-12. Figure 9-13. Figure 10-1. Figure 11-1.
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Figure 12-1. Figure 12-2. Figure 12-3. Figure 12-4. Figure 12-5. Figure 12-6. Figure 12-7. Figure 12-8. Figure 12-9. Figure 12-10. Figure 12-11. Figure 12-12. Figure 12-13. Figure 12-14. Figure 12-15. Figure 12-16. Figure 12-17. Figure 12-18. Figure 12-19. Figure 12-20. Figure 12-21. Figure 12-22. Figure 12-23. Figure 12-24. Figure 12-25. Figure 12-26. Figure 12-27. Figure 12-28. Figure 12-29. Figure 12-30. Figure 12-31. Figure 12-32. Figure 12-33. Figure 12-34. Figure 12-35. Figure 12-36. Figure 12-37.
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Figure 13-5. Figure 13-6. Figure 13-7. Figure 13-8. Figure 13-9. Figure 13-10. Figure 13-11. Figure 13-12. Figure 13-13. Figure 14-1. Figure 14-2. Figure 14-3. Figure 14-4. Figure 14-5. Figure 14-6. Figure 14-7. Figure 14-8. Figure 14-9. x Fast Transfer Mode Block Diagram ................................................................. 13-6 Fast Transfer Read Timing [Mode 00] ............................................................ 13-7 Fast Transfer Write Timing [Mode 00] ...........................
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Tables Table 1-1. Table 1-2. Table 1-3. Table 2-1. Table 2-2. Table 4-1. Table 4-2. Table 4-3. Table 5-1. Table 5-2. Table 5-3. Table 5-4. Table 5-5. Table 5-6. Table 5-7. Table 5-8. Table 5-9. Table 5-10. Table 5-11. Table 5-12. Table 5-13. Table 5-14. Table 5-14. Table 5-15. Table 5-16. Table 5-17. Table 5-18. Table 5-19. Table 6-1. Table 6-2. Table 6-3. Table 6-4. Table 6-5. EZ-USB TRM v1.9 USB PIDs........................................................................................................
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Table 7-1. Table 7-2. Table 7-3. Table 7-4. Table 7-5. Table 7-6. Table 7-7. Table 7-8. Table 7-9. Table 7-10. Table 7-11. Table 7-12. Table 7-13. Table 7-14. Table 7-15. Table 7-16. Table 7-17. Table 7-18. Table 7-19. Table 7-20. Table 7-21. Table 7-22. Table 8-1. Table 8-2. Table 9-1. Table 9-2. Table 9-3. Table 10-1. Table 10-2. Table 10-3. Table 10-4. Table 12-1. Table 12-2. Table 12-3. Table 12-4. Table 12-5. Table 12-6. Table 13-1. Table 13-2. xii The Eight Bytes in a USB SETUP Packet ..............
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Table 13-3. Table 13-4. Table 13-5. Table 13-6. Table 13-7. EZ-USB TRM v1.9 Program Memory Read..................................................................................... 13-2 Data Memory Read........................................................................................... 13-2 Data Memory Write .......................................................................................... 13-3 Fast Data Write .................................................................................
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xiv List of Tables EZ-USB TRM v1.
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1 Introducing EZ-USB 1.1 Introduction Like a well designed automobile or appliance, a USB peripheral’s outward simplicity hides internal complexity. There’s a lot going on “under the hood” of a USB device, which gives the user a new level of convenience. For example: • A USB device can be plugged in anytime, even when the PC is turned on. • When the PC detects that a USB device has been plugged in, it automatically interrogates the device to learn its capabilities and requirements.
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This chapter introduces some key USB concepts and terminology that should make reading the rest of this Technical Reference Manual easier. 1.2 EZ-USB Block Diagrams +5V D+ D- Serial Interface Engine (SIE) bytes bytes USB Interface GND USB Connector Program & Data RAM IO Ports General Purpose Microprocessor USB Transceiver EZ-USB Figure 1-1.
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+5V D+ D- Serial Interface Engine (SIE) bytes bytes GND USB Connector USB Interface Program & Data RAM General Purpose Microprocessor USB Transceiver IO Ports Address Bus Data Bus External Memory, FIFOS, etc. EZ-USB Figure 1-2. AN2131Q (80 pin) Simplified Block Diagram Figure 1-2 illustrates the An2131Q, an 80-pin version of the EZ-USB family. In addition to the 24 IO pins, it contains a 16-bit address bus and an 8-bit data bus for external memory expansion.
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1.4 Tokens and PIDs In this manual, you will read statements like, “When the host sends an IN token...” or “The device responds with an ACK.” What do these terms mean? A USB transaction consists of data packets identified by special codes called Packet IDs or PIDs. A PID signifies what kind of packet is being transmitted. There are four PID types, as shown in Table 1-1. Table 1-1.
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PID that arrives with the data, either DATA0 or DATA1. When sending data, the host or device sends alternating DATA0-DATA1 PIDs. By comparing the Data PID with the state of the internal toggle bit, the host or device can detect a corrupted handshake packet. SETUP tokens are unique to CONTROL transfers. They preface eight bytes of data from which the peripheral decodes host Device Requests. SOF tokens occur once per millisecond, denoting a USB frame. There are three handshake PIDs: ACK, NAK, and STALL.
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into the host side, the PC. If USB had been defined as peer-to-peer, every USB device would have required more intelligence, raising cost. Here are two important consequences of the “host is master” concept: 1.5.1 Receiving Data from the Host To send data to a USB peripheral, the host issues an OUT token followed by the data. If the peripheral has space for the data, and accepts it without error, it returns an ACK to the host. If it is busy, it instead sends a NAK.
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1.8 EZ-USB Transfer Types USB defines four transfer types. These match the requirements of different data types delivered over the bus. (Section 1.13, "EZ-USB Endpoints" explains how the EZ-USB family supports the four transfer types.) 1.8.1 Bulk Transfers A E I D N N D D R P C R C 5 Token Packet D A T A 1 C R C 1 6 Payload Data Data Packet A E O D N U D D T R P A C K D A T A 0 C R C 5 Token Packet H/S Pkt Payload Data Data Packet C R C 1 6 A C K H/S Pkt Figure 1-4.
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1.8.3 Isochronous Transfers A E I D N N D D R P D A T A 0 C R C 5 C R C 1 6 Payload Data Token Packet Data Packet Figure 1-6. An Isochronous Transfer Isochronous data is time-critical and used for streaming data like audio and video. Time of delivery is the most important requirement for isochronous data. In every USB frame, a certain amount of USB bandwidth is allocated to isochronous transfers. To lighten the overhead, isochronous transfers have no handshake (ACK/NAK/STALL), and no retries.
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Control transfers consist of two or three stages. The SETUP stage contains eight bytes of USB CONTROL data. An optional DATA stage contains more data, if required. The STATUS (or handshake) stage allows the device to indicate successful completion of a control operation. 1.9 Enumeration Your computer is ON. You plug in a USB device, and the Windows cursor switches to an hourglass, and then back to a cursor.
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1.10 The USB Core A E O D N U D D T R P C R C 5 Token Packet D A T A 1 C R C 1 6 Payload Data Data Packet A C K H/S Pkt A E O D N U D D T R P C R C 5 D A T A 0 Token Packet Payload Data Data Packet C R C 1 6 A C K H/S Pkt Payload Data Serial Interface Engine (SIE) D+ D- USB Tranceiver Payload Data A C K Figure 1-8. What the SIE Does Every USB device has a Serial Interface Engine (SIE). The SIE connects to the USB data lines D+ and D-, and delivers bytes to and from the USB device.
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One of the most important features of the EZ-USB family is that it is soft. Instead of requiring ROM or other fixed memory, it contains internal program/data RAM that is downloaded over the USB itself to give the device its unique personality. This make modifications, specification revisions, and updates a snap. The EZ-USB family can connect as a USB device and download code into internal RAM, all while its internal 8051 is held in RESET.
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The 8051 communicates with the SIE using a set of registers, which occupy the top of the on-chip RAM address space. These registers are grouped and described by function in individual chapters of this reference manual, and summarized in register order in Chapter 12, "EZ-USB Registers." The EZ-USB 8051 has two duties. First, it participates in the protocol defined in the Universal Serial Bus Specification Version 1.1, “Chapter 9, USB Device Framework.
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1.13.1 EZ-USB Bulk Endpoints Bulk endpoints are unidirectional—one endpoint address per direction. Therefore endpoint 2-IN is addressed differently than endpoint 2-OUT. Bulk endpoints use maximum packet sizes (and therefore buffer sizes) of 8, 16, 32, or 64 bytes. EZ-USB provides fourteen bulk endpoints, divided into seven IN endpoints (endpoint 1-IN through 7-IN), and seven OUT endpoints (endpoint 1-OUT through 7-OUT). Each of the fourteen endpoints has a 64-byte buffer.
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1.13.3 EZ-USB Interrupt Endpoints Interrupt endpoints are almost identical to bulk endpoints. Fourteen EZ-USB endpoints (EP1-EP7, IN, and OUT) may be used as interrupt endpoints. Interrupt endpoints have maximum packet sizes up to 64, and contain a “polling interval” byte in their descriptor to tell the host how often to service them. The 8051 transfers data over interrupt endpoints in exactly the same way as for bulk endpoints. Interrupt endpoints are described in Chapter 6, "EZ-USB Bulk Transfers." 1.13.
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1.15 Interrupts The EZ-USB enhanced 8051 adds seven interrupt sources to the standard 8051 interrupt system. Three of the added interrupts are used internally, and the others are available on device pins. INT2 is used for all USB interrupts. INT3 is used by the I2C interface. A third interrupt is used for remote wakeup indication. The EZ-USB core automatically supplies jump vectors (Autovectors) for its USB interrupts to save the 8051 from having to test bits to determine the source of the interrupt.
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1.17 EZ-USB Product Family The EZ-USB family is available in various pinouts to serve different system requirements and costs. Table 1-2 shows the feature set for each member of the EZ-USB Series 2100 Family. Table 1-2. EZ-USB Series 2100 Family Part Number RAM Size AN2121S AN2122S Key Features Data Bus I/O Rate Prog or Port B Bytes/s Max I/Os Package Max UART (Async) Speed (Kbaud) Power Saving Option IBN/ STOP ISO Support Endpoints 4KB Y 32 Port B 600K 16 S = 44 PQFP 115.
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48-pin Variants There are two 48-pin devices: AN2122T AN2126T The four extra pins are used as follows: • • PA7, PA6, and PA0 are GPIO pins. This makes five of the eight PORTA pins available (all except PA1-PA3). CPU12MHZ - This input controls the speed of the 8051: - tied high 12 MHz - tied low 24 MHz Bulk Endpoints The AN2122 and AN2126 have a reduced set of thirteen bulk endpoints (see Section 6.1, "Introduction").
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1.20 Pin Descriptions PC7/RD# VCC GND PB1/T2EX PB0/T2 PB2/RxD1 PB3/TxD1 D0 D1 D2 D3 PB4/INT4 PB5/INT5# PB6/INT6 PB7/T2out GND D4 D5 D6 BKPT D7 VCC SDA GND Figures 1-9 through 1-13 are pin descriptions by package type. Table 1-3 describes the pins by pin function.
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VCC DISCON# USBD+ USBD- PA5/FRD# PA4/FWR# GND WAKEUP# SCL SDA GND 44 43 42 41 40 39 38 37 36 35 34 GND 1 33 VCC CLK24 2 32 BKPT GND 3 31 PB7/T2OUT GND 4 30 PB6/INT6 GND 5 29 PB5/INT5# GND 6 28 PB4/INT4 AGND 7 27 PB3/TxD2 XIN 8 26 PB2/RxD2 XOUT 9 25 PB1/T2EX AVCC 10 24 PB0/T2 VCC 11 23 GND 19 20 PC6/WR# 21 22 VCC 18 PC7/RD# 17 PC5/T1 PC0/RxD0 16 PC4/T0 RESET 15 PC3/INT1# 14 PC2/INT0# 13 PC1/TxD0 12 GND 44 PQFP 10 x 10 mm
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VCC DISCON# USBD+ USBD- PA5/FRD# PA4/FWR# GND WAKEUP# SCL SDA GND 44 43 42 41 40 39 38 37 36 35 34 GND 1 33 VCC CLK24 2 32 BKPT GND 3 31 D7 GND 4 30 D6 GND 5 29 D5 GND 6 28 D4 AGND 7 27 D3 XIN 8 26 D2 XOUT 9 25 D1 AVCC 10 24 D0 VCC 11 23 GND 17 18 19 20 21 22 PC5/T1 PC6/WR# PC7/RD# VCC PC0/RxD0 16 PC4/T0 RESET 15 PC3/INT1# 14 PC2/INT0# 13 PC1/TxD0 12 GND 44 PQFP 10 x 10 mm Figure 1-11.
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PA5/FRD# PA4/FWR# 43 42 41 40 39 GND PA6/RxD0OUT 44 SDA USBD45 SCL USBD+ 46 WAKEUP# DISCON# 47 GND VCC 48 38 37 GND 1 36 VCC CLK24 2 35 BKPT GND 3 34 PA0/T0OUT GND 4 33 PB7/T2OUT GND 5 32 PB6/INT6 GND 6 31 PB5/INT5# AGND 7 30 PB4/INT4 PA7/RxD1OUT 8 29 PB3/TxD1 XIN 9 28 PB2/RxD1 XOUT 10 27 PB1/T2EX AVCC 11 26 PB0/T2 VCC 12 25 GND 17 18 19 20 21 22 23 PC2/INT0# PC3/INT1# PC4/T0 PC5/T1 PC6/WR# PC7/RD# 24 VCC 16 PC1/TxD0 15 CPU
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VCC DISCON# USBD+ USBD- PA6/RxD0OUT PA5/FRD# PA4/FWR# GND WAKEUP# SCL SDA GND 48 47 46 45 44 43 42 41 40 39 38 37 GND 1 36 VCC CLK24 2 35 BKPT GND 3 34 PA0/T0OUT GND 4 33 D7 GND 5 32 D6 GND 6 31 D5 AGND 7 30 D4 PA7/RxD1OUT 8 29 D3 XIN 9 28 D2 XOUT 10 27 D1 AVCC 11 26 D0 VCC 12 25 GND 48 TQFP 17 18 19 20 21 22 23 PC2/INT0# PC3/INT1# PC4/T0 PC5/T1 PC6/WR# PC7/RD# 24 VCC 16 PC1/TxD0 15 PC0/RxD0 14 CPU12MHZ GND 13 RE
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Table 1-3. EZ-USB Series 2100 Pinouts by Pin Function 2125S 2121S 2126S 2131Q 2122S 2122T 2126T 2135S 2131S 2136S Name Type Default Description 21 10 10 11 11 AVCC Power N/A Analog Vcc. This signal provides power to the analog section of the chip. 18 7 7 7 7 AGND Power N/A Analog Ground. Connect to ground with as short a path as possible. 1 43 43 47 47 DISCON# Output HI Disconnect. This pin is controlled by two bits, DISCOE and DISCON. When DISCOE=0, the pin floats.
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Table 1-3. EZ-USB Series 2100 Pinouts by Pin Function 2125S 2121S 2126S 2131Q 2122S 2122T 2126T 2135S 2131S 2136S Name Type Default Description 24 N/A N/A N/A N/A EA Input N/A External Access. If this signal is active (high), the 8051 fetches code from external memory instead of the internal program RAM. If EA=0, the 8051 fetches code from external memory starting at 0x1B40 (AN2131). 19 8 8 9 9 XIN Input N/A Crystal Input.
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Table 1-3. EZ-USB Series 2100 Pinouts by Pin Function 2125S 2121S 2126S 2131Q 2122S 2122T 2126T 2135S 2131S 2136S Name Type Default Description 71 N/A N/A N/A N/A PA3 or CS# I/O I (PA3) Multiplexed pin whose function is selected by the CS bit of the PORTACFG register. If CS=0, the pin is the bi-directional I/O port pin PA3. If CS=1, the pin is an active-low chip select for external memory.
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Table 1-3. EZ-USB Series 2100 Pinouts by Pin Function 2125S 2121S 2126S 2131Q 2122S 2122T 2126T 2135S 2131S 2136S Name Type Default Description 44 24 N/A 26 N/A PB0 or T2 I/O I (PB0) Multiplexed pin whose function is selected by the T2 bit of the PORTBFCG register. If T2=0, the pin is the bi-directional I/O port bit PB0. If T2=1, the pin is the active-high T2 signal from 8051 Timer2, which provides the input to Timer2 when C/T2=1. When C/T2=0, Timer2 does not use this pin.
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Table 1-3. EZ-USB Series 2100 Pinouts by Pin Function 2125S 2121S 2126S 2131Q 2122S 2122T 2126T 2135S 2131S 2136S 55 31 N/A 33 N/A Name Type Default Description PB7 or T2OUT I/O I (PB7) Multiplexed pin whose function is selected by the T2OUT bit of the PORTBCFG register. If T2OUT=0, the pin is the bi-directional I/O port bit PB7. If T2OUT=1, the pin is the active-high T2OUT signal from 8051 Timer2. T2OUT is active (high) for one clock cycle when Timer/Counter 2 overflows.
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Table 1-3. EZ-USB Series 2100 Pinouts by Pin Function 2125S 2121S 2126S 2131Q 2122S 2122T 2126T 2135S 2131S 2136S Name Type Default Description 40 20 20 22 22 PC6 or WR# I/O I (PC6) Multiplexed pin whose function is selected by the WR bit of the PORTCCFG register. If WR=0, the pin is the bi-directional I/O port bit PC6. If WR=1, the pin is the active-low write signal for external memory.
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2 EZ-USB CPU 2.1 Introduction The EZ-USB built-in microprocessor, an enhanced 8051 core, is fully described in Appendices A-C. This chapter introduces the processor, its interface to the EZ-USB core, and describes architectural differences from a standard 8051. 2.2 8051 Enhancements The enhanced 8051 core uses the standard 8051 instruction set. Instructions execute faster than with the standard 8051 due to two features: • Wasted bus cycles are eliminated.
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2.3 EZ-USB Enhancements The EZ-USB chip provides additional enhancements outside the 8051. These include: • Fast external transfers (Autopointer, Fast Transfer Mode) • Vectored USB interrupts (Autovector) • Separate buffers for SETUP and DATA portions of a CONTROL transfer. • Breakpoint Facility. 2.4 EZ-USB Register Interface The 8051 communicates with the EZ-USB core through a set of memory mapped registers.
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2.5 EZ-USB Internal RAM FF 80 7F 00 Upper 128 bytes Indirect Addr SFR Space Direct Addr Lower 128 bytes Direct Addr Figure 2-1. 8051 Registers Like the standard 8051, the EZ-USB 8051 core contains 128 bytes of register RAM at 007F, and a partially populated SFR register space at 80-FF. An additional 128 indirectly addressed registers (sometimes called “IDATA”) are also available at 80-FF.
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• An output enable bit that causes the IO pin to be driven from the output latch. • An alternate function bit that determines whether the pin is general IO or a special 8051 or EZ-USB function. The SFRs associated with 8051 ports 0-3 are not implemented in EZ-USB. These SFR addresses include P0 (0x80), P1 (0x90), P2 (0xA0), and P3 (0xB0). Because P2 is not implemented, the MOVX@R0/R1 instruction takes the upper address byte from an added Special Function Register (SFR) at location 0x92.
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2.8 Power Control The EZ-USB core implements a power-down mode that allows it to be used in USB bus powered devices that must draw no more than 500 µA when suspended. Power control is accomplished using a combination of 8051 and EZ-USB core resources. The mechanism by which EZ-USB powers down for suspend, and then re-powers to resume operation, is described in detail in Chapter 11, “EZ-USB Power Management.” A suspend operation uses three 8051 resources, the idle mode and two interrupts.
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2.9 SFRs The EZ-USB family was designed to keep 8051 coding as standard as possible, to allow easy integration of existing 8051 software development tools. The added 8051 SFR registers and bits are summarized in Table 2-2. Table 2-2.
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2.10 Internal Bus Members of the EZ-USB family that provide pins to expand 8051 memory provide separate non-multiplexed 16-bit address and 8-bit data busses. This differs from the standard 8051, which multiplexes eight device pins between three sources: IO port 0, the external data bus, and the low byte of the address bus. A standard 8051 system with external memory requires a de-multiplexing address latch, strobed by the 8051 ALE (Address Latch Enable) pin.
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Page 2-8 Chapter 2. EZ-USB CPU EZ-USB TRM v1.
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3 EZ-USB Memory 3.1 Introduction EZ-USB devices divide RAM into two regions, one for code and data, and the other for USB buffers and control registers. 7FFF Registers/Bulk Buffers 7B40 USB Control Registers (192 bytes) 27FF 1F40/7F40 1F3F/7F3F 16 x 64-byte Bulk Endpoint Buffers (1,024 bytes) Data (RD/WR) RAM If ISODISAB=1 2000 1FFF 1FFF/7FFF Registers/Bulk Buffers 1B40/7B40 1B40 1B3F Data (RD/WR) RAM Code(PSEN) RAM if EA=0 (6,976 bytes) 0000 Figure 3-1.
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3.2 8051 Memory Figure 3-1 illustrates the two internal EZ-USB RAM regions. 6,976 bytes of general-purpose RAM occupy addresses 0x0000-0x1B3F. This RAM is loadable by the EZ-USB core or I2C bus EEPROM, and contains 8051 code and data. The EZ-USB EA (External Access) pin controls where the bottom segment of code (PSEN) memory is located—inside (EA=0) or outside (EA=1) the EZ-USB chip.
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1F40 1F00 1EC0 1E80 1E40 1E00 1DC0 1D80 1D40 1D00 1CC0 1C80 1C40 1C00 1BC0 1B80 1B40 1B3F EP0IN EP0OUT EP1IN EP1OUT EP2IN EP2OUT EP3IN EP3OUT EP4IN EP4OUT EP5IN EP5OUT EP6IN EP06UT EP7IN EP07OUT Code/Data RAM 0000 Figure 3-3. Unused Bulk Endpoint Buffers (Shaded) Used as Data Memory In the example shown in Figure 3-3, only endpoints 0-IN through 3-IN are used for the USB function, so the data RAM (shaded) can be extended to 0x1D7F.
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3.3 Expanding EZ-USB Memory The 80-pin EZ-USB package provides a 16-bit address bus, an 8-bit bus, and memory control signals PSEN#, RD#, and WR#. These signals are used to expand EZ-USB memory.
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The internal block at 0x7B40-0x7FFF (labeled “Registers”) contains the bulk buffer memory and EZ-USB control registers. As previously mentioned, they are aliased at 0x1B400x1FFF to allow adding unused bulk buffer RAM to general-purpose memory. 8051 code should access this memory only at the 0x7B40-0x7BFF addresses.
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FFFF Inside EZ-USB Outside EZ-USB External Data Memory (RD,WR) 8000 7B40 Registers(RD,WR) (Note 1) External Code Memory (PSEN) External Data Memory (RD, WR) 2000 1FFF 1F3F 1B40 Unused Bulk Buffers (RD,WR) (Note 1) Data (RD,WR) 0000 Note 1: OK to populate data memory here--RD#, WR#, CS# and OE# are inactive. Figure 3-5. EZ-USB Memory Map with EA=1 When EA=1 (Figure 3-5), all code (PSEN) memory is external. All internal EZ-USB RAM is data memory.
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3.5 EZ-USB ROM Versions The EZ-USB 8-KB Masked ROM and 32-KB Masked ROM memory maps are shown in Figures 3-6 and 3-7. Outside EZ-USB Inside EZ-USB FFFF External Data Memory (RD,WR) 8000 7B40 External Code Memory (PSEN) Registers(RD,WR) (Note 1) External Data Memory (RD, WR) 2000 0800 07FF 0000 Internal Code Memory(PSEN) Data (RD,WR) (Note 2) (Note 1) Note 1: OK to populate data memory here, but no RD# or WR# strobes are generated.
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Outside EZ-USB Inside EZ-USB FFFF External Data Memory (RD,WR) 8000 7FFF 7B40 Registers(RD,WR) (Note 1) Internal Code Memory(PSEN) 1000 0FFF External Code Memory (PSEN) Data (RD,WR) External Data Memory (RD, WR) (Note 2) (Note 1) 0000 Note 1: OK to populate data memory here, but no RD# or WR# strobes are generated. Note 2: OK to populate code memory here, but no PSEN# strobe is generated. Figure 3-7.
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4 EZ-USB Input/Output 4.1 Introduction The EZ-USB chip provides two input-output systems: • A set of programmable IO pins • A programmable I2C Controller This chapter begins with a description of the programmable IO pins, and shows how they are shared by a variety of 8051 and EZ-USB alternate functions such as UART, timer and interrupt signals. The I2C controller uses the SCL and SDA pins, and performs two functions: • General-purpose 8051 use • Boot loading from an EEPROM Note 2.2-KB to 4.
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4.2 IO Ports OE OUT reg Pin PINS Figure 4-1. EZ-USB Input/Output Pin The EZ-USB family implements its IO ports using memory-mapped registers. This is in contrast to a standard, which uses SFR bits for input/output. Figure 4-1 shows the basic structure of an EZ-USB IO pin. Twenty-four IO pins are grouped into three 8-bit ports named PORTA, PORTB, and PORTC. The AN2131Q has all three ports, while the AN2131S has PORTB, PORTC, and two PORTA bits.
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Table 4-1.
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Alternate Function Output Alternate Function Output OE OE Pin OUT reg Pin PINS OUT reg PINS PORTCFG=0 (port) PORTCFG=1 (alternate function) Figure 4-2. Alternate Function is an OUTPUT Referring to Figure 4-2, when PORTCFG=0, the IO port is selected. In this case the alternate function (shaded) is disconnected and the pin functions exactly as shown in Figure 4-1. When PORTCFG=1, the alternate function is connected to the IO pin and the output register and buffer are disconnected.
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4.
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I2C Controller 4.4 The USB core contains an I 2C controller for boot loading and general-purpose I 2C bus interface. This controller uses the SCL (Serial Clock) and SDA (Serial Data) pins. I2C Controller describes how the boot load operates at power-on to read the contents of an external serial EEPROM to determine the initial EZ-USB FX configuration. The boot loader operates automatically, while the 8051 is held in reset. The last section of this chapter describes the operating details of the boot loader.
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Multiple I 2C Bus Masters — The EZ-USB chip acts only as an I 2C bus master, never a slave. However, the 8051 can detect a second master by checking for BERR=1 (Section 4.7, "Status Bits"). start SDA SA3 SA2 SA1 SA0 DA2 DA1 DA0 R/W ACK D7 D6 SCL 1 2 3 4 5 6 7 8 9 10 11 Figure 4-6. Addressing an I2C Peripheral The first byte of an I 2C bus transaction contains the address of the desired peripheral.
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I2CS 7FA5 I2C Control and Status b7 b6 b5 b4 b3 b2 b1 b0 START STOP LASTRD ID1 ID0 BERR ACK DONE I2DAT 7FA6 I2C Data b7 b6 b5 b4 b3 b2 b1 b0 D7 D6 D5 D4 D3 D2 D1 D0 Figure 4-7. FC Registers The 8051 uses the two registers shown in Figure 4-7 to conduct I2C transfers. The 8051 transfers data to and from the I2C bus by writing and reading the I2DAT register. The 12CS register controls I2C transfers and reports various status conditions.
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or I2DAT until the STOP bit returns low. In the 2122/2126 only, an interrupt request is available to signal that STOP bit transmission is complete. 4.6.3 LASTRD To read data over the I2C bus, an I2C master floats the SDA line and issues clock pulses on the SCL line. After every eight bits, the master drives SDA low for one clock to indicate ACK. To signal the last byte of the read transfer, the master floats SDA at ACK time to instruct the slave to stop sending.
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ACK bit at the same time it sets DONE=1. The ACK bit should be ignored for read transfers on the bus. 4.7.3 BERR This bit indicates an I2C bus error. BERR=1 indicates that there was bus contention, which results when an outside device drives the bus LO when it shouldn’t, or when another bus master wins arbitration, taking control of the bus. BERR is cleared when the 8051 reads or writes the I2DAT register. 4.7.4 ID1, ID0 These bits are set by the boot loader (Section 4.
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4.9 Receiving I2C Data To read a multiple-byte data record, follow these steps: 1. Set the START bit. 2. Write the peripheral address and direction=1 (for read) to I2DAT. 3. Wait for DONE=1*. If BERR=1 or ACK=0, terminate by setting STOP=1. 4. Read I2DAT and discard the data. This initiates the first burst of nine SCL pulses to clock in the first byte from the slave. 5. Wait for DONE=1*. If BERR=1, terminate by setting STOP=1. 6. Read the data from I2DAT. This initiates another read transfer. 7.
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I2C Boot Loader 4.10 When the EZ-USB chip comes out of reset, the EZ-USB boot loader checks for the presence of an EEPROM on its I2C bus. If an EEPROM is detected, the loader reads the first EEPROM byte to determine how to enumerate (specifically, whether to supply ID information from the EZ-USB core or from the EEPROM). The various enumeration modes are described in Chapter 5, "EZ-USB Enumeration and ReNumeration.
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Table 4-2. Strap Boot EEPROM Address Lines to These Values Bytes Example EEPROM A2 A1 A0 16 24LC00* N/A N/A N/A 128 24LC01 0 0 0 256 24LC02 0 0 0 4K 24LC32 0 0 1 8K 24LC64 0 0 1 * This EEPROM does not have address pins The I2C controller performs a three-step test at power-on to determine whether a one-byteaddress or a two-byte-address EEPROM is attached. This test proceeds as follows: 1.
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The results of this power-on test are reported in the ID1 and ID0 bits, as shown in Table 4-3. Table 4-3. Results of Power-On I2C Test ID1 ID0 Meaning 0 0 No EEPROM detected 0 1 One-byte-address load EEPROM detected 1 0 Two-byte-address load EEPROM detected 1 1 Not used Other EEPROM devices (with device address of 1010) can be attached to the I2C bus for general purpose 8051 use, as long as they are strapped for address other than 000 or 001.
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5 EZ-USB Enumeration and ReNumeration 5.1 Introduction The EZ-USB chip is soft. 8051 code and data is stored in internal RAM, which is loaded from the host using the USB interface. Peripheral devices that use the EZ-USB chip can operate without ROM, EPROM, or FLASH memory, shortening production lead times and making firmware updates a breeze.
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Another Use for the Default USB Device The Default USB Device is established at power-on to set up a USB device capable of downloading firmware into EZ-USB RAM. Another useful feature of the EZ-USB default device is that 8051 code can be written to support the already-configured Generic USB device. Before bringing the 8051 out of reset, the EZ-USB core enables certain endpoints and reports them to the host via descriptors.
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For purposes of downloading 8051 code, the Default USB Device requires only CONTROL endpoint zero. Nevertheless, the USB default machine is enhanced to support other endpoints as shown in Figure 5-1 (note the alternate settings 1 and 2). This enhancement is provided to allow the developer to get a head start generating USB traffic and learning the USB system.
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5.3 EZ-USB Core Response to EP0 Device Requests Table 5-2 shows how the EZ-USB core responds to endpoint zero requests when ReNum=0. Table 5-2.
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As shown in Table 5-2, after enumeration, the EZ-USB core responds to the following host requests. • Set or clear an endpoint stall (Set/Clear Feature-Endpoint). • Read the stall status for an endpoint (Get_Status_Endpoint). • Set/Read an 8-bit configuration number (Set/Get_Configuration). • Set/Read a 2-bit interface alternate setting (Set/Get_Interface). • Download or upload 8051 RAM.
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Table 5-4. Firmware Upload Byte Field Value Meaning 0 bmRequest 0xC0 Vendor Request, IN 1 bRequest 0xA0 “Firmware Load” 2 wValueL AddrL Starting Address 3 wValueH AddrH 4 wIndexL 0x00 5 wIndexH 0x00 6 wLengthL LenL 7 wLengthH LenH 8051 Response None required Number of Bytes These requests are always handled by the EZ-USB core (ReNum=0 or 1). This means that 0xA0 is reserved by the EZ-USB chip, and therefore should never be used for a vendor request.
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5.5 Enumeration Modes When the EZ-USB chip comes out of reset, the EZ-USB core makes a decision about how to enumerate based on the contents of an external EEPROM on its I2C bus. Table 5-5 shows the choices. In Table 5-5, PID means Product ID, VID means Version ID, and DID means Device ID. Table 5-5. EZ-USB Core Action at Power-Up First EEPROM byte EZ-USB Core Action Not 0xB0 or 0xB2 Supplies descriptors, PID/VID/DID from EZ-USB Core. Sets ReNum=0.
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The Other Half of the I2C Story The EZ-USB I2C controller serves two purposes. First, as described in this chapter, it manages the serial EEPROM interface that operates automatically at power-on to determine the enumeration method. Second, once the 8051 is up and running, the 8051 can access the I2C controller for general-purpose use. This makes a wide range of standard I2C peripherals available to an EZ-USB system.
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Reminder The EZ-USB core uses the Table 5-6 data for enumeration only if the ReNum bit is zero. If ReNum=1, enumeration data is supplied by 8051 code. 5.7 Serial EEPROM Present, First Byte is 0xB0 Table 5-7.
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5.8 Serial EEPROM Present, First Byte is 0xB2 If, at power-on, the EZ-USB core detects an EEPROM connected to its I2C port with the value 0xB2 at address 0; the EZ-USB core loads the EEPROM data into EZ-USB RAM. It also sets the ReNum bit to 1, causing device requests to be fielded by the 8051 instead of the EZ-USB core. The EEPROM data format is shown in Table 5-8. Table 5-8.
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One or more data records follow, starting at EEPROM address 7. The maximum value of Length H is 0x03, allowing a maximum of 1,023 bytes per record. Each data record consists of a length, a starting address, and a block of data bytes. The last data record must have the MSB of its Length H byte set to 1. The last data record consists of a single-byte load to the CPUCS register at 0x7F92. Only the LSB of this byte is significant— 8051RES (CPUCS.0) is set to zero to bring the 8051 out of reset.
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Internal Logic DISCON DISCON# pin DISCOE Figure 5-2. Disconnect Pin Logic The logic for the DISCON and DISCOE bits is shown in Figure 5-2. To simulate a USB disconnect, the 8051 writes the value 00001010 to USBCS. This floats the DISCON# pin, and provides an internal DISCON signal to the USB core that causes it to perform disconnect housekeeping. To re-connect to USB, the 8051 writes the value 00000110 to USBCS.
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5.10 Multiple ReNumerations The 8051 can ReNumerate anytime. Once use for this capability might be to fine tune an isochronous endpoint’s bandwidth requests by trying various descriptor values and ReNumerating. 5.11 Default Descriptor Tables 5-9 through 5-19 show the descriptor data built into the EZ-USB core. The tables are presented in the order that the bytes are stored. Table 5-9.
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Table 5-10.
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Table 5-12.
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Table 5-14.
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Table 5-14.
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Table 5-15.
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Interface 0, alternate setting 1 has six isochronous endpoints with maximum packet sizes of 16 bytes. This is a low bandwidth setting. Table 5-16.
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Table 5-18.
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Table 5-19.
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Page 5-22 Chapter 5. EZ-USB CPU EZ-USB TRM v1.
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6 EZ-USB Bulk Transfers 6.1 Introduction A E I D N N D D R P C R C 5 Token Packet D A T A 0 Payload Data C R C 1 6 Data Packet A E I D N N D D R P A C K C R C 5 Token Packet H/S Pkt D A T A 1 Payload Data Data Packet C R C 1 6 A C K H/S Pkt Figure 6-1. Two BULK Transfers, IN and OUT EZ-USB provides sixteen endpoints for BULK, CONTROL, and INTERRUPT transfers, numbered 0-7 as shown in Table 6-1. This chapter describes BULK and INTERRUPT transfers.
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The USB specification allows maximum packet sizes of 8, 16, 32, or 64 bytes for bulk data, and 1 - 64 bytes for interrupt data. EZ-USB provides the maximum 64 bytes of buffer space for each of its sixteen endpoints 0-7 IN and 0-7 OUT. Six of the bulk endpoints, 2-IN, 4-IN, 6-IN, 2-OUT, 4-OUT, and 6-OUT may be paired with the next consecutively numbered endpoint to provide double-buffering, which allows one data packet to be serviced by the 8051 while another is in transit over USB.
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Registers Associated with a Bulk IN endpoint (EP2IN shown as example) Initialization IN07VAL 7 6 5 4 3 Data transfer 2 1 0 IN2BUF Endpoint Valid (1=valid) USBPAIR o67 o45 o23 i67 i45 64 Byte Endpoint Buffer i23 Endpoint Pairing (1=paired) IN07IEN 7 6 5 4 3 2 1 0 IN2BC Byte Count Interrupt Enable (1=enabled) Busy and Stall Interrupt Control IN2CS B S IN07IRQ Control & Status 7 6 5 4 3 2 1 0 Interrupt Request (write 1 to clear) Registers Associated with a Bulk O
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Bulk IN Transfers ... 1 2 3 4 5 H D H H D A I D N D R E N D P D A T A 1 C R C 5 C R C 1 6 Payload Data Data Packet Token Packet ... 5 H A I D N D R E N D P C R C 5 Token Packet C R C 5 Token Packet H/S Pkt (INnBC loaded) 4 A E I D N N D D R P A C K .. . N A K H/S Pkt EPnIN Interrupt, INnBSY=0 6 7 8 D H D N A K A E I D N N D D R P ...
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IN tokens (4) and (7) until the data is ready. Eventually, the 8051 fills the endpoint buffer with data, and then loads the endpoint’s byte count register (INnBC) with the number of bytes in the packet (6). Loading the byte count re-arms the given endpoint. When the next IN token arrives (7) the USB core transfers the next data packet (8). 6.3 Interrupt Transfers Interrupt transfers are handled just like bulk transfers.
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The 8051 now loads the next 64 bytes into IN2BUF and then loads the EPINBC register with 64 for the next two transfers. For the last portion of the transfer, the 8051 loads the final 28 bytes into IN2BUF, and loads IN2BC with 28. This completes the transfer. Initialization Note When the EZ-USB chip comes out of RESET, or when the USB host issues a bus reset, the EZ-USB core unarms IN endpoint 1-7 by setting their busy bits to 0.
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2 H H A E O D N U D D T R P ... D A T A 1 C R C 5 Payload Data (OUTnBC loaded, OUTnBSY=1) 4 5 D H H A E O D N U D D T R P A C K Data Packet Token Packet .. .
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host issues a NAK, indicating busy (6). The data at (5) is shaded to indicate that the USB core discards it, and does not over-write the data in the endpoint’s OUT buffer. The host continues to send OUT tokens (4, 5, and 6) that are greeted by NAKs until the buffer is ready. Eventually, the 8051 empties the endpoint buffer data, and then loads the endpoint’s byte count register (7) with any value to re-arm the USB core.
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use endpoint 2-IN as a double-buffered endpoint. This pairs the IN2BUF and IN3BUF buffers, although the 8051 accesses the IN2BUF buffer only. The 8051 sets PR2IN=1 (in the USBPAIR register) to enable pairing, sets IN2VAL=1 (in the IN07VAL register) to make the endpoint valid, and then uses the IN2BUF buffer for all data transfers. The 8051 should not write the IN3VAL bit, enable IN3 interrupts, access the EP3IN buffer, or load the IN3BC byte count register.
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6.8 Paired OUT Endpoint Status OUTnBSY=1 indicates that both endpoint buffers are empty, and no data is available to the 8051. When OUTnBSY=0, either one or both of the buffers holds USB OUT data. The 8051 can keep an internal count that increments on EPnOUT interrupts and decrements on byte count loads to determine whether one or two buffers contain data.
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2-IN/OUT (paired), 4-IN and 4-OUT can use 0x1B40-0x1CBF as data memory. Chapter 3 gives full details of the EZ-USB memory map. Note AN2122 endpoint memory starts at 0x1C00 and AN2126 endpoint memory starts at address 0x7C00. Note Uploads or Downloads to unused bulk memory can be done only at the Mirrored (low) addresses shown in Table 6-3. 6.10 Data Toggle Control The EZ-USB core automatically maintains the data toggle bits during bulk, control and interrupt transfers.
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The IO bit selects the endpoint direction (1=IN, 0=OUT), and the EP2-EP1-EP0 bits select the endpoint number. The Q bit, which is read-only, indicates the state of the data toggle for the selected endpoint. Writing R=1 sets the data toggle to DATA0, and writing S=1 sets the data toggle to DATA1. Note At the present writing, there appears to be no reason to set a data toggle to DATA1. The S bit is provided for generality.
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6.11 Polled Bulk Transfer Example The following code illustrates the EZ-USB registers used for a simple bulk transfer. In this example, 8051 register R1 keeps track of the number of endpoint 2-IN transfers and register R2 keeps track of the number of endpoint 2-OUT transfers (mod-256). Every endpoint 2-IN transfer consists of 64 bytes of a decrementing count, with the first byte replaced by the number of IN transfers and the second byte replaced by the number of OUT transfers.
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The code at lines 2-7 fills the endpoint 2-IN buffer with 64 bytes of a decrementing count. Two 8-bit counts are initialized to zero at lines 9 and 10. An endpoint 2-IN transfer is armed at lines 11-13, which load the endpoint 2-IN byte count register IN2BC with 64. Then the program enters a polling loop at lines 15-20, where it checks two flags for endpoint 2 servicing. Lines 15-17 check the endpoint 2-IN busy bit in IN2CS bit 1. Lines 1820 check the endpoint 2-OUT busy bit in OUT2CS bit 1.
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6.13 Bulk Endpoint Interrupts All USB interrupts activate the 8051 INT 2 interrupt. If enabled, INT2 interrupts cause the 8051 to push the current program counter onto the stack, and then execute a jump to location 0x43, where the programmer has inserted a jump instruction to the interrupt service routine (ISR).
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The vector values are four bytes apart. This allows the programmer to build a jump table to each of the interrupt service routines. Note that the jump table must begin on a page (256 byte) boundary because the first vector starts at 00. If Autovectoring is not used (AVEN=0), the IVEC register may be directly inspected to determine the USB interrupt source (see Section 9.11, "Autovector Coding").
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1. Set up the jump table.
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2. Write the INT2 interrupt vector. ; ----------------; Interrupt Vectors ; ----------------org ljmp 43h USB_Jump_Table ; int2 is the USB vector ; Autovector will replace byte 45 Figure 6-8. INT2 Interrupt Vector 3. Write the interrupt service routine. Put it anywhere in memory and the jump table in step 1 will automatically jump to it.
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4. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 Write the endpoint 2 transfer program. loop: jnb clr got_EP2_data,loop got_EP2_data ; clear my flag ; ; The user sent bytes to OUT2 endpoint using the USB Control Panel. ; Find out how many bytes were sent.
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OUT2BC is used as a loop counter in R7 to transfer the exact number of bytes that were received over endpoint 2-OUT. When the transfer is complete, the program loads the endpoint 2-IN byte count register IN2BC with the number of loaded bytes (from R6) to arm the next endpoint 2-IN transfer in lines 29-31. Finally, the 8051 loads any value into the endpoint 2 OUT byte count register OUT2BC to arm the next OUT transfer in lines 35-36. Then the program loops back to check for more endpoint 2-OUT data. 5.
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6.15 Enumeration Note The code in this example is complete, and runs on the EZ-USB chip. You may be wondering about the missing step, which reports the endpoint characteristics to the host during the enumeration process. The reason this code runs without any enumeration code is that the EZ-USB chip comes on as a fully-functional USB device with certain endpoints already configured and reported to the host. Endpoint 2 is included in this default configuration.
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6.16 The Autopointer Bulk endpoint data is available in 64-byte buffers in EZ-USB RAM. In some cases it is preferable to access bulk data as a FIFO register rather than as a RAM. The EZ-USB core provides a special data pointer which automatically increments when data is transferred. Using this Autopointer, the 8051 can access any contiguous block of internal EZ-USB RAM as a FIFO.
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The 8051 code example in Figure 6-13 uses the Autopointer to transfer a block of eight data bytes from the endpoint 4 OUT buffer to internal 8051 memory.
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Note The Autopointer works only with internal program/data RAM. It does not work with memory outside the chip, or with internal RAM that is made available when ISODISAB=1. See Section 8.9.1, "Disable ISO" for a description of the ISODISAB bit.
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7 EZ-USB Endpoint Zero 7.1 Introduction Endpoint Zero has special significance in a USB system. It is a CONTROL endpoint, and is required by every USB device. Only CONTROL endpoints accept special SETUP tokens that the host uses to signal transfers that deal with device control. The USB host sends a repertoire of standard device requests over endpoint zero. These standard requests are fully defined in Chapter 9 of the USB Specification.
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7.
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The STATUS stage consists of an empty data packet with the opposite direction of the data stage, or an IN if there was no data stage. This empty data packet gives the device a chance to ACK or NAK the entire CONTROL transfer. The 8051 writes a “1” to a bit call HSNAK (Handshake NAK) to clear it and instruct the EZ-USB core to ACK the STATUS stage. The HSNAK bit is used to hold off completing the CONTROL transfer until the device has had time to respond to a request.
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USB registers starting at SETUPDAT. The EZ-USB core takes care of any re-tries if it finds any errors in the SETUP data. These two interrupt request bits are set by the EZUSB core, and must be cleared by firmware. An 8051 program responds to the SUDAV interrupt request by either directly inspecting the eight bytes at SETUPDAT or by transferring them to a local buffer for further processing.
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Two bits in the USBIEN (USB Interrupt Enable) register enable the SETUP Token (SUTOKIE) and SETUP Data interrupts. The actual interrupt request bits are in the USBIRQ (USB Interrupt Requests) register. They are called STOKIR (SETUP Token Interrupt Request) and SUDAVIR (SETUP Data Interrupt Request). The EZ-USB core transfers the eight SETUP bytes into eight bytes of RAM at SETUPDAT.
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Table 7-2.
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7.3.1 Get Status The USB Specification version 1.0 defines three USB status requests. A fourth request, to an interface, is indicated in the spec as “reserved.” The four status requests are: • Remote Wakeup (Device request) • Self-Powered (Device request) • Stall (Endpoint request) • Interface request (“reserved”) The EZ-USB core activates the SUDAV interrupt request to tell the 8051 to decode the SETUP packet and supply the appropriate status information.
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As Figure 7-4 illustrates, the 8051 responds to the SUDAV interrupt by decoding the eight bytes the EZ-USB core has copied into RAM at SETUPDAT. The 8051 answers a Get_Status request (bRequest=0) by loading two bytes into the IN0BUF buffer and loading the byte count register IN0BC with the value “2.” The EZ-USB core transmits these two bytes in response to an IN token. Finally, the 8051 clears the HSNAK bit (by writing “1” to it) to instruct the EZ-USB core to ACK the status stage of the transfer.
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Each bulk endpoint (IN or OUT) has a STALL bit in its Control and Status register (bit 0). If the CPU sets this bit, any requests to the endpoint return a STALL handshake rather than ACK or NAK. The Get Status-Endpoint request returns the STALL state for the endpoint indicated in byte 4 of the request. Note that bit 7 of the endpoint number EP (byte 4) specifies direction. Endpoint zero is a CONTROL endpoint, which by USB definition is bi-directional. Therefore, it has only one stall bit.
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Table 7-5. Get Status-Interface Byte 0 Field Value Meaning 8051 Response bmRequestType 0x81 IN, Endpoint Load two bytes into IN0BUF “Get Status” Byte 0 : zero 1 bRequest 0x00 2 wValueL 0x00 3 wValueH 0x00 4 wIndexL 0x00 5 wIndexH 0x00 6 wLengthL 0x02 7 wLengthH 0x00 Byte 1 : zero Two bytes requested Get_Status/Interface is easy: the 8051 returns two zero bytes through IN0BUF and clears the HSNAK bit.
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Table 7-7. Set Feature-Endpoint (Stall) Byte 0 1 2 3 4 5 6 7 Field bmRequestType bRequest wValueL wValueH wIndexL wIndexH wLengthL wLengthH Value Meaning 0x02 OUT, Endpoint 0x03 “Set Feature” 0x00 Feature Selector: STALL 0x00 EP 0x00 0x00 0x00 8051 Response Set the STALL bit for the indicated endpoint: EP(n): 0x00-0x07: OUT0-OUT7 0x80-0x87: IN0-IN7 The only Set_Feature/Endpoint request presently defined in the USB Specification is to stall an endpoint.
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7.3.3 Clear Feature Clear Feature is used to disable remote wakeup or to clear a stalled endpoint. Table 7-8. Clear Feature-Device (Clear Remote Wakeup Bit) Byte 0 Field Value Meaning bmRequestType 0x00 OUT, Device 1 bRequest 0x01 “Clear Feature” 2 wValueL 0x01 Feature Selector: Remote Wakeup 3 wValueH 0x00 4 wIndexL 0x00 5 wIndexH 0x00 6 wLengthL 0x00 7 wLengthH 0x00 8051 Response Clear the remote wakeup bit Table 7-9.
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(over EP0-IN) such information as what device driver to load, how many endpoints it has, its different configurations, alternate settings it may use, and informative text strings about the device. The EZ-USB core provides a special Setup Data Pointer to simplify 8051 service for Get_Descriptor requests. The 8051 loads this 16-bit pointer with the beginning address of the requested descriptor, clears the HSNAK bit (by writing “1” to it), and the EZ-USB core does the rest.
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The CONTROL transaction starts in the usual way, with the EZ-USB core transferring the eight bytes in the SETUP packet into RAM at SETUPDAT and activating the SUDAV interrupt request. The 8051 decodes the Get_Descriptor request, and responds by clearing the HSNAK bit (by writing “1” to it), and then loading the SUDPTR registers with the address of the requested descriptor.
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index. This constitutes the second phase of the three-phase CONTROL transfer. The core Packetizes the data into multiple data transfers as necessary. 4. Automatically checks for errors and re-transmits data packets if necessary. 5. Responds to the third (handshake) phase of the CONTROL transfer to terminate the operation. The Setup Data Pointer can be used for any Get_Descriptor request; for example, Get_Descriptor-String.
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7.3.4.3 Get Descriptor-String Table 7-12.
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Table 7-14. Set Descriptor-Configuration Byte Field Value Meaning 8051 Response 0 bmRequestType 0x00 OUT, Device Read configuration descriptor 1 bRequest 0x07 “Set_Descriptor” data over OUT0BUF 2 wValueL 0x00 3 wValueH 0x02 4 wIndexL 0x00 5 wIndexH 0x00 6 wLengthL LenL 7 wLengthH LenH Descriptor Type: Configuration Table 7-15.
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Configurations, Interfaces, and Alternate Settings Configurations, Interfaces, and Alternate Settings Device A USB device has one or more configuration. Only one configuration is active at any time. A configuration has one or more interface, all of which are concurrently active. Multiple interfaces allow different hostside device drivers to be associated with different portions of a USB device. Each interface has one or more alternate setting.
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7.3.6 Set Configuration Table 7-16.
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7.3.8 Set Interface This confusingly named USB command actually sets and reads back alternate settings for a specified interface. USB devices can have multiple concurrent interfaces. For example a device may have an audio system that supports different sample rates, and a graphic control panel that supports different languages. Each interface has a collection of endpoints. Except for endpoint 0, which each interface uses for device control, endpoints may not be shared between interfaces.
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7.3.9 Get Interface Table 7-19.
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7.3.11 Sync Frame Table 7-20.
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7.3.12 Firmware Load The USB endpoint zero protocol provides a mechanism for mixing vendor-specific requests with the previously described standard device requests. Bits 6:5 of the bmRequest field are set to 00 for a standard device request, and to 10 for a vendor request. Table 7-21.
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Page 7-24 Chapter 7. EZ-USB CPU EZ-USB TRM v1.
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8 EZ-USB Isochronous Transfers 8.1 Introduction Isochronous endpoints typically handle time-critical, streamed data that is delivered or consumed in byte-sequential order. Examples might be audio data sent to a DAC over USB, or teleconferencing video data sent from a camera to the host. Due to the bytesequential nature of this data, the EZ-USB chip makes isochronous data available as a single byte that represents the head or tail of an endpoint FIFO.
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8.2 Isochronous IN Transfers IN transfers travel from device to host. Figure 8-2 shows the EZ-USB registers and bits associated with isochronous IN transfers.
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The EZ-USB core uses the ISOSEND0 bit to determine what to do if: • The 8051 does not load any bytes to an INnDATA register during the previous frame, and • An IN token for that endpoint arrives from the host. If ISOSEND0=0 (the default value), the EZ-USB core does not respond to the IN token. If ISOSEND0=1, the EZ-USB core sends a zero-length data packet in response to the IN token. Which action to take depends on the overall system design.
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Registers Associated with an ISO OUT endpoint (EP15OUT shown as example) Data transfer Initialization OUTISOVAL 15 14 13 12 11 10 9 8 OUT15DATA 7 6 A9 A8 A7 A6 A5 A4 0 0 USBIRQ FIFO Start Address (see text) USBIEN 7 6 5 4 3 2 1 SOFIE (1=enabled) 4 3 2 1 0 1 0 Data from USB Endpoint Valid (1=valid) OUT15ADDR 5 7 6 5 4 3 2 SOFIR (1=clear request) 0 OUT15BCH 7 6 5 4 3 2 9 8 Received Byte Count (H) OUT15BCL 7 6 5 4 3 2 1 0 Received Byte Coun
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To respond to the SOF interrupt, the 8051 clears the USB interrupt (8051 INT2), and clears the SOFIR bit by writing one to it. Then, the 8051 reads data from the appropriate OUTnDATA FIFO register(s). The 8051 can check an error bit in the ISOERR register to determine if a CRC error occurred for the endpoint data. Isochronous data is never present, so the firmware must decide what to do with bad-CRC data. 8.
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Table 8-1.
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0100 0100 0010 0010 0010 0010 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 ; 0000 0040 0044 0048 0048 0048 0048 0048 0048 0088 008C 0090 0090 0090 0090 0090 EP8INSZ EP8OUTSZ EP9INSZ EP9OUTSZ EP10INSZ EP10OUTSZ EP11INSZ EP11OUTSZ EP12INSZ EP12OUTSZ EP13INSZ EP13OUTSZ EP14INSZ EP14OUTSZ EP15INSZ EP15OUTSZ equ equ equ equ equ equ equ equ equ equ equ equ equ equ equ equ 256 256 16 16 16 16 0 0 0 0 0 0 0 0 0 0 ; Iso FIFO sizes in bytes 8OUTAD 9OUTAD 10OUTAD 11OUTAD 12OUTAD 13OUTAD 14OUTAD 15OUTAD 8INAD
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8.5 Isochronous Transfer Speed The amount of data USB can transfer during a 1-ms frame is slightly more than 1,000 bytes per frame (1,500 bytes theoretical, without accounting for USB overhead and bus utilization). A device’s actual isochronous transfer bandwidth is usually determined by how fast the CPU can move data in and out of its isochronous endpoint FIFOs. The 8051 code example in Figure 8-6 shows a typical transfer loop for moving external FIFO data into an IN endpoint FIFO.
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8.6 Fast Transfers EZ-USB has a special fast transfer mode for applications that use external FIFOs connected to the EZ-USB data bus. These applications typically require very high transfer speeds in and out of EZ-USB endpoint buffers. EZ-USB Registers (Addressed as external RAM) DPTR movx a,@dptr movx @dptr,a Accumulator Figure 8-7. 8051 MOVX Instructions The 8051 transfers data to and from EZ-USB registers and RAM using the MOVX (move external) instruction (Figure 8-7).
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Fast Bulk Transfers The EZ-USB core provides a special auto-incrementing data pointer that makes the fast transfer mechanism available for bulk transfers. The 8051 loads a 16-bit RAM address into the AUTOPTRH/L registers, and then accesses RAM data as a FIFO using the AUTODATA register. Section 6.16, "The Autopointer" describes this special pointer and register. 8.6.1 Fast Writes ISO OUT FIFO movx a,@dptr DPTR FWR# D[7..0] External FIFO or ASIC Accumulator Figure 8-8.
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8.6.2 Fast Reads ISO IN FIFO movx @dptr,a DPTR FRD# D[7..0] External FIFO or ASIC Accumulator Figure 8-9. Fast Transfer, Outside Memory to EZ-USB Fast reads are illustrated in Figure 8-9. When the fast mode is enabled, the DPTR points to an isochronous OUT FIFO register, and the 8051 executes the “movx @dptr,a” instruction, the EZ-USB core breaks the data path from the accumulator to the IN FIFO register, and instead writes the IN FIFO using outside data from D[7..0].
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RMOD1-RMOD0 for read strobes and WMOD1-WMOD0 for write strobes, as shown in Figure 8-11 (write) and Figure 8-12 (read). Note When using the fast transfer feature, be sure to enable the FRD# and FWR# strobe signals in the PORTACFG register. 8.7.1 Fast Write Waveforms tC L 4 1 .6 6 n s C LK 24 D [7 ..0 ] O utput s tre tc h = 0 0 0 s tre tc h = 0 0 0 F W R # [0 0 ] s tre tc h = 0 0 0 F W R # [0 1 ] s tre tc h = 0 0 0 F W R # [1 0 ] s tre tc h = 0 0 0 F W R # [1 1 ] D [7 ..
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The timing choices for fast write pulses (FWR#) are shown in Figure 8-11. The 8051 can extend the output data and widths of these pulses by setting cycle stretch values greater than zero in the 8051 Clock Control Register CKCON (at SFR location 0x8E). The top five waveforms show the fastest write timings, with a stretch value of 000, which performs the write in eight 8051 clocks. The bottom five waveforms show the same waveforms with a stretch value of 001. 8.7.2 Fast Read Waveforms tCL 41.
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FRD# strobes[00] and [01], along with the OSC24 clock signal are typically used to connect to an external synchronous FIFO. The on-clock-wide read strobe ensures that the FIFO address advances only once per clock. The second strobe [01] is for FIFOs that put data on the bus one clock after the read strobe. Stretch values above 000 serve only to extend the 8051 cycle times, without affecting the width of the FRD# strobe.
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times 19 cycles, or 2,432 cycles. The 1,024 byte transfer would take 403 µs, less than half of the 1-ms USB frame time. If still faster time is required, the routine can be modified to put more of the MOVX instructions in-line. For example, with 16 in-line MOVX instructions, the transfer time for 1,024 bytes would be 35 cycles times 64 loops or 2,240 cycles, or 371 µs, an 8% speed improvement over the eight instruction loop. 8.
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ISOCTL register bits shown as MBZ (must be zero) must be written with zeros. The PPSTAT bit toggles every SOF, and may be written with any value (no effect). Therefore, to disable the isochronous endpoints, the 8051 should write the value 0x01 to the ISOCTL register. Caution! If you use this option, be absolutely certain that the host never sends isochronous data to your device. Isochronous data directed to a disabled isochronous endpoint system will cause unpredictable operation.
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8.10 ISO IN Response with No Data The ISOSEND0 bit (bit 7 in the USBPAIR register) is used when the EZ-USB chip receives an isochronous IN token while the IN FIFO is empty. If ISOSEND0=0 (the default value) the EZ-USB core does not respond to the IN token. If ISOSEND0=1, the EZ-USB core sends a zero-length data packet in response to the IN token. Which action to take depends on the overall system design. The ISOSEND0 bit applies to all of the isochronous IN endpoints, IN-8 through IN-15. 8.
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Page 8-18 Chapter 8. EZ-USB CPU EZ-USB TRM v1.
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9 EZ-USB Interrupts 9.1 Introduction The EZ-USB enhanced 8051 responds to the interrupts shown in Table 9-1. Interrupt sources that are not present in the standard 8051 are shown as checked in the “New” column. The three interrupts used by the EZ-USB core are shown in bold type. Table 9-1.
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USB Signaling - These include 16 bulk endpoint interrupts, three interrupts not specific to a particular endpoint (SOF), Suspend, USB Reset), and two interrupts for CONTROL transfers (SUTOK, SUDAV). These interrupts share the USB interrupt (INT2). The AN2122/26 versions have an interrupt indicating that a bulk packet was NAKd. I2C Transfers - (INT3). 9.3 Wakeup Interrupt Chapter 10, "EZ-USB Resets" describes suspend-resume signaling in detail, along with a code example that uses the Wakeup interrupt.
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tb EICON.5 ; enable Resume interrupt The 8051 reads the RESUME interrupt request bit in EICON.4, and clears the interrupt request by writing a zero to EICON.4. Resume_isr: clr EICON.4 ; clear the 8051 W/U ; interrupt request reti EZ-USB TRM v1.9 Chapter 9.
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9.4 USB Signaling Interrupts Figure 9-2 shows the 21 USB requests that share the 8051 USB (INT2) interrupt. The bottom IRQ, EP7-OUT, is expanded in the diagram to show the logic associated with each USB interrupt request. Vector 05, not shown in the diagram, exists only in the AN2122/ AN2126, and is described later in this chapter.
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Referring to the logic inside the dotted lines, each USB interrupt source has an interrupt request latch. The EZ-USB core sets an IRQ bit, and the 8051 clears an IRQ bit by writing a “1” to it. The output of each latch is ANDed with an IEN (Interrupt Enable) bit and then ORd with all the other USB interrupt request sources. The EZ-USB core prioritizes the USB interrupts, and constructs an Autovector, which appears in the AVEC register. The interrupt vector values IV[4..
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Figure 9-3 illustrates a typical USB ISR for endpoint 2-IN. USB_ISR: push push push push push push dps dpl dph dpl1 dph1 acc mov clr mov a,EXIF acc.4 EXIF,a ; FIRST clear the USB (INT2) interrupt request mov mov movx dptr,#IN07IRQ a,#00000100b @dptr,a ; now clear the USB interrupt request ; use IN2 as example ; ; Note: EXIF reg is not 8051 bit-addressable ; ; ; (perform interrupt routine stuff) ; pop acc pop dph1 pop dpl1 pop dph pop dpl pop dps ; reti Figure 9-3.
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IN07IRQ Endpoints 0-7 IN Interrupt Requests 7FA9 b7 b6 b5 b4 b3 b2 b1 b0 IN7IR IN6IR IN5IR IN4IR IN3IR IN2IR IN1IR IN0IR OUT07IRQ Endpoints 0-7 OUT Interrupt Requests 7FAA b7 b6 b5 b4 b3 b2 b1 b0 OUT7IR OUT6IR OUT5IR OUT4IR OUT3IR OUT2IR OUT1IR OUT0IR USBIRQ USB Interrupt Request 7FAB b7 b6 b5 b4 b3 b2 b1 b0 - - - USESIR SUSPIR SUTOKIR SOFIR SUDAVIR IN07IEN Endpoints 0-7 IN Interrupt Enables 7FAC b7 b6 b5 b4 b3 b2 b1 b0 IN7IEN IN6IEN IN5I
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The USBIEN and USBIRQ registers control the first five interrupts shown in Figure 9-2. The IN07IEN and OUT07 registers control the remaining 16 USB interrupts, which correspond to the 16 bulk endpoints IN0-IN7 and OUT0-OUT7. The 21 USB interrupts are now described in detail. 9.5 SUTOK, SUDAV Interrupts SETUP Stage S A E C E D N R T D D C U R P 5 P Token Packet SUTOK Interrupt D A T A 0 8 bytes Setup Data C R C 1 6 Data Packet A C K H/S Pkt SUDAV Interrupt Figure 9-5.
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9.6 SOF Interrupt F C S R R O N C F O 5 Token Pkt Figure 9-6. A Start Of Frame (SOF) Packet USB Start of Frame interrupt requests occur every millisecond. When the EZ-USB core receives an SOF packet, it copies the eleven-bit frame number (FRNO in Figure 9-6) into the USBFRAMEH and USBFRAMEL registers, and activates the SOF interrupt request. The 8051 services all isochronous endpoint data as a result of the SOF interrupt. 9.
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The EZ-USB core sets an endpoint’s interrupt request bit when the endpoint’s busy bit (in the endpoint CS register) goes low, indicating that the endpoint buffer is available to the 8051. For example, when endpoint 4-OUT receives a data packet, the busy bit in the OUT4CS register goes low, and OUT07IRQ.4 goes high, requesting the endpoint 4-OUT interrupt. 9.10 USB Autovectors The USB interrupt is shared by 21 interrupt sources.
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Table 9-3. A Typical USB Jump Table Table Offset 9.
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2. Code the jump table with jump instructions to each individual USB interrupt service routine. This table has two important requirements, arising from the format of the AVEC byte (zero-based, with 2 LSBs set to 0): • It must begin on a page boundary (address 0xNN00). • The jump instructions must be four bytes apart. • The interrupt service routines can be placed anywhere in memory. • Write initialization code to enable the USB interrupt (INT2), and Autovectoring.
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9.12 I2C Interrupt EZ-USB 8051 EIE.1 DONE RD or WR I2DAT register S S R R I2C Interrupt Request I2CS I2DAT 8051 I2C Interrupt (INT3) EXIF.5(rd) EXIF.5(0) START STOP LASTRD ID1 ID0 BERR ACK DONE D7 D6 D5 D4 D3 D2 D1 D0 Figure 9-8. I2C Interrupt Enable Bits and Registers Chapter 4, "EZ-USB Input/Output" describes the 8051 interface to the EZ-USB I2C controller. The 8051 uses two registers, I2CS (I2C Control and Status) and I2DAT (I2C Data) to transfer data over the I2C bus.
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In some situations, the host may send IN tokens before the 8051 has loaded and armed an IN endpoint. To alert the 8051 that an IN endpoint is being pinged, the AN2122/26 add a set of interrupts, one per IN endpoint, that indicate that an IN endpoint just sent a NAK to the host. This happens when the host sends an IN token and the IN endpoint does not have data (yet) for the host. The new interrupt is called “IBN,” for IN Bulk NAK.
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I2C STOP Complete Interrupt - (AN2122/AN2126 only) 9.14 I2CMODE 7FA7 I2C Mode b7 b6 b5 b4 b3 b2 b1 b0 0 0 0 0 0 0 STOPIE 0 R R R R R R R/W R 0 0 0 0 0 0 0 0 Figure 9-11. I2C Mode Register The I2C interrupt includes one additional interrupt source in the AN2122/AN2126, a 1-0 transition of the STOP bit. To enable this interrupt, set the STOPIE bit in the I2CMODE register. The 8051 determines the interrupt source by checking the DONE and STOP bits in the I2CS register.
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The two registers that the 8051 uses to control I2C transfers are shown above. In the EZUSB family, an I2C interrupt request occurs on INT3 whenever the DONE bit (I2CS.0) makes a 0-to-1 transition. This interrupt signals the 8051 that the I2C controller is ready for another command. The 8051 concludes I2C transfers by setting the STOP bit (I2CS.6). When the STOP condition has been sent over the I2C bus, the I2C controller resets I2CS.6 to zero.
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10 EZ-USB Resets 10.1 Introduction The EZ-USB chip has three resets: • A Power-On Reset (POR), which turns on the EZ-USB chip in a known state. • An 8051 reset, controlled by the EZ-USB core. • A USB bus reset, sent by the host to reset a device. This chapter describes the effects of these three resets. 10.2 EZ-USB Power-On Reset (POR) RES 8051 Vcc CPUCS.0 (1 at PWR ON) RESET RES EZ-USB Core 24 MHz USB Bus Reset 48 MHz XIN 12 MHz Oscillator PLL XOUT ÷2 CLK24 Figure 10-1.
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connected to Vcc through a 1 µF capacitor and to GND through a 10-K resistor (Figure 10-1). The oscillator and PLL are unaffected by the state of the RESET pin. The CLK24 signal is active while RESET = HI. When RESET returns LO, the activity on the CLK24 pin depends on whether or not the EZ-USB chip is in suspend state. If in suspend, CLK24 stops. Resumption of USB bus activity or asserting the WAKEUP# pin LO re-starts the CLK24 signal.
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From Table 10-1, at power-on: • Endpoint data buffers and byte counts are un-initialized (1,2). • The 8051 is held in reset, and the CLK24 pin is enabled (3). • All port pins are configured as input ports (4-6). • USB interrupts are disabled, and USB interrupt requests are cleared (7-8). • Bulk IN and OUT endpoints are unarmed, and their stall bits are cleared (9). The EZ-USB core will NAK IN or OUT tokens while the 8051 is reset. OUT endpoints are enabled when the 8051 is released from reset.
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10.3.1 RAM Download Once enumerated, the host can download code into the EZ-USB RAM using the “Firmware Load” vendor request (Chapter 7, "EZ-USB Endpoint Zero"). The last packet loaded writes 0 to the CPUCS register, which clears the 8051 RESET bit. Note The other bit in the CPUCS register, CLK24OE, is writable only by the 8051, so the host writing a zero byte to this register does not turn off the CLK24 signal. 10.3.2 EEPROM Load Chapter 5 describes the EEPROM boot loads in detail.
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section, this particular reset is called an “8051 Reset,” and should not be confused with the POR described in Section 10.2, "EZ-USB Power-On Reset (POR)." This discussion applies only to the condition where the EZ-USB chip is powered, and the 8051 is reset by the host setting the CPUCS register to 0. The basic USB device configuration remains intact through an 8051 reset. Valid endpoints remain valid, the USB function address remains the same, and the IO ports retain their configurations and values.
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Table 10-2.
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Note from item 12 that the ReNum bit is unchanged after a USB bus reset. Therefore, if a device has ReNumerated and loaded a new personality, it retains the new personality through a USB bus reset. 10.6 EZ-USB Disconnect Table 10-3.
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• The function address is reset to zero (13). • The configuration is reset to zero (19). • Alternate settings are reset to zero (20). 10.7 Reset Summary Table 10-4.
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11 EZ-USB Power Management 11.1 Introduction The USB host can suspend a device to put it into a power-down mode. When the USB signals a SUSPEND operation, the EZ-USB chip goes through a sequence of steps to allow the 8051 to first turn off external power-consuming subsystems, and then enter an ultra-low-power mode by turning off its oscillator. Once suspended, the EZ-USB chip is awakened either by resumption of USB bus activity, or by assertion of its WAKEUP# pin.
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11.2 Suspend 12 MHz STOP Oscillator PLL 48 MHz div by 2 CLK24 PCON.0 8051 INT2 No USB activity for 3 msec. USB "SUSPEND" Interrupt Figure 11-2. EZ-USB Suspend Sequence A USB device recognizes SUSPEND as 3 ms of a bus idle (“J”) state. The EZ-USB core alerts the 8051 by asserting the USB (INT2) interrupt and the SUSPEND interrupt vector. This gives the 8051 code a chance to perform power SUSPEND interrupt vector.
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The 8051 code responds to the SUSPEND interrupt by taking the following steps: 1. Performs any necessary housekeeping such as shutting off external power-consuming devices. 2. Sets bit 0 of the PCON SFR (Special Function Register). This has two effects: • The 8051 enters its idle mode, which is exited by any interrupt. • The 8051 sends an internal signal to the EZ-USB core which causes it to turn off the oscillator and PLL.
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The EZ-USB oscillator re-starts when: • USB bus activity resumes (shown as “USB Resume” in Figure 11-3), or • External logic asserts the EZ-USB WAKEUP# pin low. After an oscillator stabilization time, the EZ-USB core asserts the 8051 Resume interrupt (Figure 9-1). This causes the 8051 to exit its idle mode. The Resume interrupt is the highest priority 8051 interrupt. It is always enabled, unaffected by the EA bit.
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Note If your design does not use remote wakeup, tie the WAKEUP# pin high. Holding the WAKEUP# pin low inhibits the EZ-USB chip from suspending. When a USB device is suspended, the hub driver is tri-stated, and the bus pullup and pulldown resistors cause the bus to assume the “J,” or idle state. A suspended device signals a remote wakeup by asserting the “K” state for 10-15 ms. The 8051 controls this using the SIGRSUME bit in the USBCS register.
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Page 11-6 Chapter 11. EZ-USB Power Management EZ-USB TRM v1.
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12 EZ-USB Registers 12.1 Introduction This section describes the EZ-USB registers in the order they appear in the EZ-USB memory map. The registers are named according to the following conventions. Most registers deal with endpoints. The general register format is DDDnFFF, where: DDD is endpoint direction, IN or OUT with respect to the USB host. n is the endpoint number, where: FFF • “07” refers to endpoints 0-7 as a group. • 0-7 refers to each individual BULK/INTERRUPT/CONTROL endpoint.
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Other Conventions USB ADDR VAL FRAME PTR Indicates a global (not endpoint-specific) USB function. Is an address. Means “valid.” Is a frame count. Is an address pointer.
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12.2 Bulk Data Buffers INnBUF,OUTnBUF Endpoint 0-7 IN/OUT Data Buffers 1B40-1F3F* b7 b6 b5 b4 b3 b2 b1 b0 D7 D6 D5 D4 D3 D2 D1 D0 R/W R/W R/W R/W R/W R/W R/W R/W x x x x x x x x * See Table 12-1 for individual endpoint buffer addresses. Figure 12-2. Bulk Data Buffers Table 12-1.
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12.3 Isochronous Data FIFOs OUTnDATA EP8OUT-EP15OUT FIFO Registers 7F60-7F67* b7 b6 b5 b4 b3 b2 b1 b0 D7 D6 D5 D4 D3 D2 D1 D0 R R R R R R R R x x x x x x x x INnDATA EP8IN-EP15IN FIFO Registers 7F68-7F6F* b7 b6 b5 b4 b3 b2 b1 b0 D7 D6 D5 D4 D3 D2 D1 D0 W W W W W W W W x x x x x x x x * See Table 12-2 for individual endpoint buffer addresses. Figure 12-3. Isochronous Data FIFOs Table 12-2.
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Sixteen addressable data registers hold data from the eight isochronous IN endpoints and the eight isochronous OUT endpoints. Reading a Data Register reads a Receive FIFO byte (USB OUT data); writing a Data Register loads a Transmit FIFO byte (USB IN data). EZ-USB TRM v1.9 Chapter 12.
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12.4 Isochronous Byte Counts OUTnBCH OUT(8-15) Byte Count High 7F70-7F7F* b7 b6 b5 b4 b3 b2 b1 b0 0 0 0 0 0 0 BC9 BC8 R R R R R R R R x x x x x x x x INnBCL OUT(8-15) Byte Count Low 7F70-7F7F* b7 b6 b5 b4 b3 b2 b1 b0 BC7 BC6 BC5 BC4 BC3 BC2 BC1 BC0 R R R R R R R R x x x x x x x x * See Table 12-3 for individual endpoint buffer addresses. Figure 12-4. Isochronous Byte Counts Table 12-3.
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The EZ-USB core uses the byte count registers to report isochronous data payload sizes for OUT data transferred from the host to the USB core. Ten bits of byte count data allow payload sizes up to 1,023 bytes. A byte count of zero is valid, meaning that the host sent no isochronous data during the previous frame. The default values of these registers are unknown. Byte counts are valid only for OUT endpoints. The byte counts indicate the number of bytes remaining in the endpoint’s Receive FIFO.
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12.5 CPU Registers CPUCS CPU Control and Status 7F92 b7 b6 b5 b4 b3 b2 b1 b0 RV3 RV2 RV1 RV0 0 0 CLK24OE 8051RES R R R R R R R/W R RV3 RV2 RV1 RV0 0 0 1 1 Figure 12-5. CPU Control and Status Register This register enables the CLK24 output and permits the host to reset the 8051 using a Firmware Download. Bit 7-4: RV[3..0] Silicon Revision These register bits define the silicon revision. Consult individual Cypress Semiconductor data sheets for values.
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12.
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Table 12-4.
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12.
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PINSA Port A Pins 7F99 b7 b6 b5 b4 b3 b2 b1 b0 PINA7 PINA6 PINA5 PINA4 PINA3 PINA2 PINA1 PINA0 R R R R R R R R x x x x x x x x PINSB Port B Pins 7F9A b7 b6 b5 b4 b3 b2 b1 b0 PINB7 PINB6 PINB5 PINB4 PINB3 PINB2 PINB1 PINB0 R R R R R R R R x x x x x x x x OUTC Port C Pins 7F98 b7 b6 b5 b4 b3 b2 b1 b0 PINC7 PINC6 PINC5 PINC4 PINC3 PINC2 PINC1 PINC0 R R R R R R R R x x x x x x x x Figure 12-8.
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OEA Port A Output Enable 7F9C b7 b6 b5 b4 b3 b2 b1 b0 OEA7 OEA6 OEA5 OEA4 OEA3 OEA2 OEA1 OEA0 R/W R/W R/W R/W R/W R/W R/W R/W x x x x x x x x OEB Port B Output Enable 7F9D b7 b6 b5 b4 b3 b2 b1 b0 OEB7 OEB6 OEB5 OEB4 OEB3 OEB2 OEB1 OEB0 R/W R/W R/W R/W R/W R/W R/W R/W x x x x x x x x OEC Port C Output Enable 7F9E b7 b6 b5 b4 b3 b2 b1 b0 OEC7 OEC6 OEC5 OEC4 OEC3 OEC2 OEC1 OEC0 R/W R/W R/W R/W R/W R/W R/W R/W x x
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12.8 230-Kbaud UART Operation - AN2122, AN2126 UART230 230-Kbaud UART Control 7F9F b7 b6 b5 b4 b3 b2 b1 b0 - - - - - - UART1 UART0 R R R R R R R/W R/W 0 0 0 0 0 0 0 0 Figure 12-10. 230-Kbaud UART Operation Register Bit 1: UART1 Universal 115/230 Kbaud operation for UART1 Bit 0: UART0 Universal 115/230 Kbaud operation for UART0 These bits, when set to “1,” connect an internal 3.69-MHz clock to UART0 and/or UART1.
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ISOCTL Isochronous Control 7FA1 b7 b6 b5 b4 b3 b2 b1 b0 - - - - PPSTAT MBZ MBZ ISODISAB R R R R R R/W R/W R/W 0 0 0 0 0 0 0 0 Figure 12-12. Isochronous Control Register Bit 3: PPSTAT Ping-Pong Status This bit indicates the isochronous buffer currently in use by the EZ-USB core. It is used only for diagnostic purposes. Bits 2,1: MBZ Must be zero These bits must always be written with zeros.
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12.10 I2C Registers I2CS 7FA5 I2C Control and Status b7 b6 b5 b4 b3 b2 b1 b0 START STOP LASTRD ID1 ID0 BERR ACK DONE R/W R/W R/W R R R R R 0 0 0 x x 0 0 0 I2DAT 7FA6 I2C Data b7 b6 b5 b4 b3 b2 b1 b0 D7 D6 D5 D4 D3 D2 D1 D0 R/W R/W R/W R/W R/W R/W R/W R/W x x x x x x x x Figure 12-14. I2C Transfer Registers The 8051 uses these registers to transfer data over the EZ-USB I2C bus.
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Bit 5: LASTRD Last Data Read To read data over the I2C bus, an I2C master floats the SDA line and issues clock pulses on the SCL line. After every eight bits, the master drives SDA low for one clock to indicate ACK. To signal the last byte of the read transfer, the master floats SDA at ACK time to instruct the slave to stop sending. This is controlled by the 8051 by setting LastRD=1 before reading the last byte of a read transfer.
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Bit 0: I2C Transfer DONE DONE The I2C controller sets this bit whenever it completes a byte transfer, right after the ACK stage. The controller also generates an I2C interrupt request (8051 INT3) when it sets the DONE bit. The I2C controller automatically clears the DONE bit and the I2C interrupt request bit whenever the 8051 reads or writes the I2DAT register.
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12.11 Interrupts IVEC Interrupt Vector 7FA8 b7 b6 b5 b4 b3 b2 b1 b0 0 IV4 IV3 IV2 IV1 IV0 0 0 R R R R R R R R 0 0 0 0 0 0 0 0 Figure 12-16. Interrupt Vector Register IVEC indicates the source of an interrupt from the USB Core. When the USB core generates an INT2 (USB) interrupt request, it updates IVEC to indicate the source of the interrupt. The interrupt sources are encoded on IV[4..0] as shown in Figure 9-2. EZ-USB TRM v1.9 Chapter 12.
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IN07IRQ Endpoint 0-7 IN Interrupt Request 7FA9 b7 b6 b5 b4 b3 b2 b1 b0 IN7IR IN6IR IN5IR IN4IR IN3IR IN2IR IN1IR IN0IR R/W R/W R/W R/W R/W R/W R/W R/W 0 0 0 0 0 0 0 0 OUT07IRQ Endpoint 0-7 OUT Interrupt Requests 7FAA b7 b6 b5 b4 b3 b2 b1 b0 OUT7IR OUT6IR OUT5IR OUT4IR OUT3IR OUT2IR OUT1IR OUT0IR R/W R/W R/W R/W R/W R/W R/W R/W x x x x x x x x Figure 12-17.
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USBIRQ USB Interrupt Request 7FAB b7 b6 b5 b4 b3 b2 b1 b0 - - IBNIR* URESIR SUSPIR SUTOKIR SOFIR SUDAVIR R/W R/W R/W R/W R/W R/W R/W R/W 0 0 0 0 0 0 0 0 * AN2122/AN2126 only. Figure 12-18. USB Interrupt Request (IRQ) Registers USBIRQ indicates the interrupt request status of the USB reset, suspend, setup token, start of frame, and setup data available interrupts. Bit 5: IBNIR IN Bulk NAK Interrupt Request This bit is in the AN2122 and AN2126 versions only.
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Bit 2: SUTOKIR SETUP Token Interrupt Request The EZ-USB core sets this bit to “1” when it receives a SETUP token. Write a “1” to this bit to clear the interrupt request. See Chapter 7, "EZ-USB Endpoint Zero" for more information on the handling of SETUP tokens. Because this bit can change state while the 8051 is in reset, it may be active when the 8051 comes out of reset, although it is reset to “0” by a power-on reset.
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IN07EN Endpoint 0-7 IN Interrupt Enables 7FAC b7 b6 b5 b4 b3 b2 b1 b0 IN7IEN IN6IEN IN5IEN IN4IEN IN3IEN IN2IEN IN1IEN IN0IEN R/W R/W R/W R/W R/W R/W R/W R/W 0 0 0 0 0 0 0 0 OUT07IEN Endpoint 0-7 OUT Interrupt Enables 7FAD b7 b6 b5 b4 b3 b2 b1 b0 OUT7IEN OUT6IEN OUT5IEN OUT4IEN OUT3IEN OUT2IEN OUT1IEN OUT0IEN R/W R/W R/W R/W R/W R/W R/W R/W x x x x x x x x Figure 12-19.
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USBIEN USB Interrupt Enable 7FAE b7 b6 b5 b4 b3 b2 b1 b0 - - IBNIE* URESIE SUSPIE SUTOKIE SOFIE SUDAVIE R/W R/W R/W R/W R/W R/W R/W R/W 0 0 0 0 0 0 0 0 * AN2122/AN2126 only. Figure 12-20. USB Interrupt Enable Register USBIEN bits gate the interrupt request to the 8051 for USB reset, suspend, SETUP token, start of frame, and SETUP data available. Bit 5: IBNIE IN bulk NAK Interrupt Enable This bit is in the AN2122 and AN2126 versions only.
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Bit 1: SOFIE Start of frame Interrupt Enable This bit is the interrupt mask for the SOFIE bit. When this bit is “1,” the interrupt is enabled, when it is “0,” the interrupt is disabled. Bit 0: SUDAVIE SETUP data available Interrupt Enable This bit is the interrupt mask for the SUDAVIE bit. When this bit is “1,” the interrupt is enabled, when it is “0,” the interrupt is disabled. EZ-USB TRM v1.9 Chapter 12.
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USBBAV Breakpoint and Autovector 7FAF b7 b6 b5 b4 b3 b2 b1 b0 - - - - BREAK BPPULSE BPEN AVEN R/W R/W R/W R/W R/W R/W R/W R/W 0 0 0 0 0 0 0 0 Figure 12-21. Breakpoint and Autovector Register Bit 3: BREAK Breakpoint enable The BREAK bit is set when the 8051 address bus matches the address held in the bit breakpoint address registers (next page). The BKPT pin reflects the state of this bit. The 8051 writes a “1” to the BREAK bit to clear it.
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IBNIRQ IN Bulk NAK Interrupt Requests 7FB0 b7 b6 b5 b4 b3 b2 b1 b0 - EP6IN EP5IN EP4IN EP3IN EP2IN EP1IN EP0IN R/W R/W R/W R/W R/W R/W R/W R/W x x x x x x x x * AN2122/AN2126 only. Figure 12-22. IN Bulk NAK Interrupt Request Register These bits are set when a bulk IN endpoint (0-6) received an IN token while the endpoint was not armed for data transfer. In this case the SIE automatically sends a NAK response, and sets the corresponding IBNIRQ bit.
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BPADDRH Breakpoint Address High 7FB2 b7 b6 b5 b4 b3 b2 b1 b0 A15 A14 A13 A12 A11 A10 A9 A8 R/W R/W R/W R/W R/W R/W R/W R/W 0 0 0 0 0 0 0 0 BPADDRL Breakpoint Address Low 7FB3 b7 b6 b5 b4 b3 b2 b1 b0 A7 A6 A5 A4 A3 A2 A1 A0 R/W R/W R/W R/W R/W R/W R/W R/W x x x x x x x x Figure 12-24. IN/OUT Interrupt Enable Registers When the current 16-bit address (code or xdata) matches the BPADDRH/BPADDRL address, a breakpoint event occurs.
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12.
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If the CONTROL transfer uses an OUT data phase, the 8051 must load a dummy byte count into OUT0BC to arm the OUT endpoint buffer. Until it does, the EZ-USB core will NAK the OUT tokens. Bit 2: INBSY IN Endpoint Busy INBSY is a read-only bit that is automatically cleared when a SETUP token arrives. The 8051 sets the INBSY bit by writing a byte count to IN0BC.
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12.13 Endpoint 1-7 Control and Status Registers Endpoints 1-7 IN and OUT are used for bulk or interrupt data. Table 12-5 shows the addresses for the control/status and byte count registers associated with these endpoints. The bi-directional CONTROL endpoint zero registers are described in Section 12.12, "Endpoint 0 Control and Status Registers." Table 12-5. Control and Status Register Addresses for Endpoints 0-7 Address EZ-USB TRM v1.
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INnCS Endpoint (1-7) IN Control and Status 7FB6-7FC2* b7 b6 b5 b4 b3 b2 b1 b0 - - - - - - INnBSY INnSTL R R R R R R R/W R/W 0 0 0 0 0 0 0 0 * See Table 12-5 for individual control/status register addresses. Figure 12-26. IN Control and Status Registers Bit 1: INnBSY IN Endpoint (1-7) Busy The BSY bit indicates the status of the endpoint’s IN Buffer INnBUF. The EZ-USB core sets BSY=0 when the endpoint’s IN buffer is empty and ready for loading by the 8051.
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Bit 0: INnSTL IN Endpoint (1-7) Stall The 8051 sets this bit to “1” to stall an endpoint, and to “0” to clear a stall. When the stall bit is “1,” the EZ-USB core returns a STALL Handshake for all requests to the endpoint. This notifies the host that something unexpected has happened. The 8051 sets an endpoint’s stall bit under two circumstances: 1. The host sends a “Set_Feature—Endpoint Stall” request to the specific endpoint. 2.
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INnBC Endpoint (1-7) IN Byte Count 7FB7-7FC3* b7 b6 b5 b4 b3 b2 b1 b0 - D6 D5 D4 D3 D2 D1 D0 R/W R/W R/W R/W R/W R/W R/W R/W x x x x x x x x * See Table 12-5 for individual byte count register addresses. Figure 12-27. IN Byte Count Registers The 8051 writes this register with the number of bytes it loaded into the IN endpoint buffer INnBUF. Writing this register also arms the endpoint by setting the endpoint BSY bit to 1. Legal values for these registers are 0-64.
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OUTnCS Endpoint (1-7) OUT Control and Status 7FC6-7FD2* b7 b6 b5 b4 b3 b2 b1 b0 - - - - - - OUTnBSY OUTnSTL R R R R R R R R/W 0 0 0 0 0 0 0 0 * See Table 12-5 for individual control/status register addresses. Figure 12-28. OUT Control and Status Registers Bit 1: OUTnBSY OUT Endpoint (1-7) Busy The BSY bit indicates the status of the endpoint’s OUT Buffer OUTnBUF. The EZ-USB core sets BSY=0 when the host data is available in the OUT buffer.
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2. The 8051 encounters any show stopper error on the endpoint, and sets the stall bit to tell the host to halt traffic to the endpoint. The 8051 clears an endpoint’s stall bit under two circumstances: 1. The host sends a “Clear_Feature—Endpoint Stall” request to the specific endpoint. 2. The 8051 receives some other indication from the host that the stall should be cleared (this is referred to as “host intervention” in the USB Specification).
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12.14 Global USB Registers SUDPTRH Setup Data Pointer High 7FD4 b7 b6 b5 b4 b3 b2 b1 b0 A15 A14 A13 A12 A11 A10 A9 A8 R/W R/W R/W R/W R/W R/W R/W R/W x x x x x x x x SUDPTRL Setup Data Pointer Low 7FD5 b7 b6 b5 b4 b3 b2 b1 b0 A7 A6 A5 A4 A3 A2 A1 A0 R/W R/W R/W R/W R/W R/W R/W R/W x x x x x x x x Figure 12-30.
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USBCS USB Control and Status 7FD6 b7 b6 b5 b4 b3 b2 b1 b0 WAKESRC - - - DISCON DISCOE RENUM SIGRSUME R/W R R R R/W R/W R/W R/W 0 0 0 0 0 1 0 0 Figure 12-31. USB Control and Status Registers Bit 7: WAKESRC Wakeup source This bit indicates that a high to low transaction was detected on the WAKEUP# pin. Writing a “1” to this bit resets it to “0.” Bit 3: DISCON Signal a Disconnect on the DISCON# pin The EZ-USB DISCON# pin reflects the complement of this bit.
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Bit 1: RENUM ReNumerate This bit controls which entity, the USB core or the 8051, handles USB device requests. When RENUM=0, the EZ-USB core handles all device requests. When RENUM=1, the 8051 handles all device requests except Set_Address. The 8051 sets RENUM=1 during a bus disconnect to transfer USB control to the 8051. The EZ-USB core automatically sets RENUM=1 under two conditions: 1. Completion of a “B2” boot load (Chapter 5, "EZ-USB Enumeration and ReNumeration"). 2.
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TOGCTL Data Toggle Control 7FD7 b7 b6 b5 b4 b3 b2 b1 b0 Q S R IO 0 EP2 EP1 EP0 R R/W R/W R/W R/W R/W R/W R/W x x x x x x x x Figure 12-32. Data Toggle Control Register Bit 7: Q Data Toggle Value Q=0 indicates DATA0 and Q=1 indicates DATA1, for the endpoint selected by the IO and EP[2..0] bits. The 8051 writes the endpoint select bits (IO and EP[2..0]), before reading this value.
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Bit 2-0: EP Select endpoint The 8051 sets these bits to select an endpoint prior to setting its R or S bit. Valid values are 0-7 to correspond to bulk endpoints IN0-IN7 and OUT0-OUT7. USBFRAMEL USB Frame Count Low 7FD8 b7 b6 b5 b4 b3 b2 b1 b0 FC7 FC6 FC5 FC4 FC3 FC2 FC1 FC0 R R R R R R R R x x x x x x x x USBFRAMEH USB Frame Count High 7FD9 b7 b6 b5 b4 b3 b2 b1 b0 0 0 0 0 0 FC10 FC9 FC8 R R R R R R R R x x x x x x x x Figure 12-33.
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FNADDR Function Address 7FDB b7 b6 b5 b4 b3 b2 b1 b0 0 FA6 FA5 FA4 FA3 FA2 FA1 FA0 R R R R R R R R x x x x x x x x Figure 12-34. Function Address Register During the USB enumeration process, the host sends a device a unique 7-bit address, which the EZ-USB core copies into this register. There is normally no reason for the CPU to know its USB device address because the USB Core automatically responds only to its assigned address.
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USBPAIR USB Endpoint Pairing 7FDD b7 b6 b5 b4 b3 b2 b1 b0 ISOSEND0 - PR6OUT PR4OUT PR2OUT PR6IN PR4IN PR2IN R/W R/W R/W R/W R/W R/W R/W R/W 0 x 0 0 0 0 0 0 Figure 12-35. USB Endpoint Pairing Register Bit 7: ISOSEND0 Isochronous Send Zero Length Data Packet The ISOSEND0 bit is used when the EZ-USB chip receives an isochronous IN token while the IN FIFO is empty. If ISOSEND0=0 (the default value), the EZ-USB core does not respond to the IN token.
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IN07VAL Endpoints 0-7 IN Valid Bits 7FDE b7 b6 b5 b4 b3 b2 b1 b0 IN7VAL IN6VAL IN5VAL IN4VAL IN3VAL IN2VAL IN1VAL IN0VAL R/W R/W R/W R/W R/W R/W R/W R/W 0 1 0 1 0 1 1 1 OUT07VAL Endpoints 0-7 OUT Valid Bits 7FDF b7 b6 b5 b4 b3 b2 b1 b0 OUT7VAL OUT6VAL OUT5VAL OUT4VAL OUT3VAL OUT2VAL OUT1VAL OUT0VAL R/W R/W R/W R/W R/W R/W R/W R/W 0 1 0 1 0 1 0 1 Figure 12-36.
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INISOVAL Isochronous IN Endpoint Valid Bits 7FE0 b7 b6 b5 b4 b3 b2 b1 b0 IN15VAL IN14VAL IN13VAL IN12VAL IN11VAL IN10VAL IN9VAL IN8VAL R/W R/W R/W R/W R/W R/W R/W R/W 0 0 0 0 0 1 1 1 OUTISOVAL b7 Isochronous OUT Endpoint Valid Bits b6 b5 b4 b3 b2 OUT15VAL OUT14VAL OUT13VAL OUT12VAL OUT11VAL OUT10VAL 7FE1 b1 b0 OUT9VAL OUT8VAL R/W R/W R/W R/W R/W R/W R/W R/W 0 0 0 0 0 1 1 1 Figure 12-37.
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12.15 Fast Transfers FASTXFR Fast Transfer Control 7FE2 b7 b6 b5 b4 b3 b2 b1 b0 FISO FBLK RPOL RMOD1 RMOD0 WPOL WMOD1 WMOD0 R/W R/W R/W R/W R/W R/W R/W R/W x x x x x x x x Figure 12-38. Fast Transfer Control Register The EZ-USB core provides a fast transfer mode that improves the8051 transfer speed between external logic and the isochronous and bulk endpoint buffers.
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Bit 2: WPOL FWR# Pulse Polarity The 8051 sets WPOL=0 for active-low FWR# pulses, and WPOL=1 for active high FWR# pulses. Bit 1-0: WMOD FWR# Pulse Mode These bits select the phasing and width of the FWR# pulse. See Figure 8-11. EZ-USB TRM v1.9 Chapter 12.
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AUTOPTRH Auto Pointer Address High 7FE3 b7 b6 b5 b4 b3 b2 b1 b0 A15 A14 A13 A12 A11 A10 A9 A8 R/W R/W R/W R/W R/W R/W R/W R/W x x x x x x x x AUTOPTRL Auto Pointer Address Low 7FE4 b7 b6 b5 b4 b3 b2 b1 b0 A7 A6 A5 A4 A3 A2 A1 A0 R/W R/W R/W R/W R/W R/W R/W R/W x x x x x x x x AUTODATA Auto Pointer Data 7FE5 b7 b6 b5 b4 b3 b2 b1 b0 D7 D6 D5 D4 D3 D2 D1 D0 R/W R/W R/W R/W R/W R/W R/W R/W x x x x x x x x Fi
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12.16 SETUP Data SETUPBUF SETUP Data Buffer (8 Bytes) 7FE8-7FEF b7 b6 b5 b4 b3 b2 b1 b0 D7 D6 D5 D4 D3 D2 D1 D0 R R R R R R R R x x x x x x x x Figure 12-40. SETUP Data Buffer This buffer contains the 8 bytes of SETUP packet data from the most recently received CONTROL transfer. The data in SETUPBUF is valid when the SUDAVIR (Setup Data Available Interrupt Request) bit is set. The 8051 responds to the SUDAV interrupt by reading the SETUP bytes from this buffer.
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12.17 Isochronous FIFO Sizes OUTnADDR ISO OUT Endpoint Start Address 7FF0-7FF7* b7 b6 b5 b4 b3 b2 b1 b0 A9 A8 A7 A6 A5 A4 0 0 R/W R/W R/W R/W R/W R/W R/W R/W x x x x x x x x INnADDR ISO IN Endpoint Start Address 7FF8-7FFF* b7 b6 b5 b4 b3 b2 b1 b0 A9 A8 A7 A6 A5 A4 0 0 R/W R/W R/W R/W R/W R/W R/W R/W x x x x x x x x * See Table 12-6 for individual start address register addresses. Figure 12-41. SETUP Data Buffer Page 12-50 Chapter 12.
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Table 12-6.
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Page 12-52 Chapter 12. EZ-USB Registers EZ-USB TRM v1.
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13 EZ-USB AC/DC Parameters 13.1 Electrical Characteristics 13.1.1 Absolute Maximum Ratings Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-65oC to +150oC Ambient Temperature Under Bias . . . . . . . . . . . . . . . . . . . .-40oC to +85oC Supply Voltage to Ground Potential . . . . . . . . . . . . . . . . . . . -0.5V to +4.0V DC Input Voltage to Any Pin . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to +5.8V 13.1.
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13.1.4 AC Electrical Characteristics Specified Conditions: Capacitive load on all pins = 30 pF 13.1.5 General Memory Timing Table 13-2. General Memory Timing Symbol Parameter Min Typ Max 41.66 Unit tCL 1/CLK24 Frequency tAV Delay from Clock to Valid Address 0 10 ns tCD Delay from CLK24 to CS# 2 15 ns tOED Delay from CLK24 to OE# 2 15 ns tWD Delay from CLK24 to WR# 2 15 ns tRD Delay from CLK24 to RD# 2 15 ns tPD Delay from CLK24 to PSEN# 2 15 ns 13.1.
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13.1.8 Data Memory Write Table 13-5. Data Memory Write Symbol Parameter tAH3 Address Hold from CLK24 tDV CLK24 to Data Valid tDVZ CLK24 to High Impedance 13.1.9 Formula Min tCL+2 43 tCL+16 57 Max Unit Notes ns 15 ns ns Fast Data Write Table 13-6. Fast Data Write Symbol Parameter Conditions Min Max Unit tCDO Clock to Data Output Delay 3 15 ns tCWO Clock to FIFO Write Output Delay 2 10 ns tPFWD Propagation Delay Difference from FIFO Write to DATA Out 1 Notes ns 13.
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tCL CLK24 tAV A [15.0] tCD tCD tOED tOED tWD tWD tRD tRD tPD tPD CS# OE# WR# RD# PSEN# Figure 13-1. External Memory Timing tCL CLK24 OE# tAA1 tAH1 tDSU1 tDH1 Figure 13-2. Program Memory Read Timing Page 13-4 Chapter 13. EZ-USB AC/DC Parameters EZ-USB TRM v1.
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tCL CLK24 RD# CS# OE# A [15.0] tAA2 tAH2 tDSU2 tDH2 D [7.0] Figure 13-3. Data Memory Read Timing tCL CLK24 CS# WR# tAH3 A [15.0] tDV tDVZ D [7.0] Figure 13-4. Data Memory Write Timing EZ-USB TRM v1.9 Chapter 13.
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EZ-USB Fast Transfer Block Diagram EZ-USB AN2131Q 80 PQFP ASIC CLK24 FIFO Clock D [7:0] D [7:0] FWR# FIFO Write Stobe FRD# FIFO Read Stobe Figure 13-5. Fast Transfer Mode Block Diagram Page 13-6 Chapter 13. EZ-USB AC/DC Parameters EZ-USB TRM v1.
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tCL CLK24 tDSU4 tDH4 Input D[7..0] tCRO FRD#[00] Figure 13-6. Fast Transfer Read Timing [Mode 00] tCL CLK24 tCDO tCDO D[7..0] Output tCWO tCWO FWR#[00] Figure 13-7. Fast Transfer Write Timing [Mode 00] EZ-USB TRM v1.9 Chapter 13.
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tCL CLK24 tDSU4 tDH4 Input D[7..0] tCRO FRD#[01] Figure 13-8. Fast Transfer Read Timing [Mode 01] tCL CLK24 tCDO D[7..0] tCDO Output tCWO tCWO FWR#[01] tPFWD Figure 13-9. Fast Transfer Write Timing [MODE 01] Page 13-8 Chapter 13. EZ-USB AC/DC Parameters EZ-USB TRM v1.
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tCL CLK24 tDSU4 tDH4 Input D[7..0] tCRO FRD#[10] Figure 13-10. Fast Transfer Read Timing [Mode 10] tCL CLK24 tCDO D[7..0] tCDO Output tCWO tCWO FWR#[10] Figure 13-11. Fast Transfer Write Timing [Mode 10] EZ-USB TRM v1.9 Chapter 13.
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tCL CLK24 tDSU4 tDH4 Input D[7..0] tCRO FRD#[11] Figure 13-12. Fast Transfer Read Timing [Mode 11] tCL CLK24 tCDO tCDO Output D[7..0] tCWO tCWO FWR#[11] tPFWD Figure 13-13. Fast Transfer Write Timing [Mode 11] Page 13-10 Chapter 13. EZ-USB AC/DC Parameters EZ-USB TRM v1.
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14 EZ-USB Packaging 14.1 44-Pin PQFP Package 13.45 12.95 10.10 9.90 8.00 REF 44 34 33 1 0.80 BSC. 23 11 12 22 Figure 14-1. 44-Pin PQFP Package (Top View) See Lead Detail 2.35 MAX 0.45 0.30 Figure 14-2. 44-Pin PQFP Package (Side View) EZ-USB TRM v1.9 Chapter 14.
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1.95 2.10 0o~7o 0.25 0.10 0.23 0.13 0.95 0.65 1.60 TYP Lead Detail: A(S=N/S) Figure 14-3. 44-Pin PQFP Package (Detail View) Page 14-2 Chapter 14. EZ-USB Packaging EZ-USB TRM v1.
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14.2 80-Pin PQFP Package 24.10 23.70 20.05 19.95 0.80 64 3.0 65 41 40 0.80 BSC. 18.10 17.70 14.05 13.95 3.0 80 PQFP 80 25 24 1.00 Ref 1 Figure 14-4. 80-Pin PQFP Package (Top View) See Lead Detail 3.04 MAX 0.42 0.32 Figure 14-5. 80-Pin PQFP Package (Side View) EZ-USB TRM v1.9 Chapter 14.
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2.66 2.76 0o~10o 0o~7o 0.25 G age Plane 8 Places 12o REF. Base Plane Seating Plane 0.28 0.18 1.00 0.80 1.95 + 0.15 Detail "A" Figure 14-6. 80-Pin PQFP Package (Detail View) Page 14-4 Chapter 14. EZ-USB Packaging EZ-USB TRM v1.
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14.3 48-Pin TQFP Package S ee L ea d D e ta il 1 .60 M A X 0 .2 7 0 .1 7 AL L D IM EN S IO N S IN M IL L IM ET ER S . Figure 14-7. 48-Pin TQFP Package (Side View) 9 .0 0 B S C . 7 .0 0 BSC. 48 37 36 1 0 .5 0 B S C . 48 T Q F P 25 12 13 24 AL L D IM EN S IO N S IN M IL L IM ET ER S . Figure 14-8. 48-Pin TQFP Package (Top View) EZ-USB TRM v1.9 Chapter 14.
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1.35 1.45 0.08 0.20 R. 0.25 Gauge Plane 0 o M IN . Base Plane Seating Plane 0.05 0.15 0.08 R . M IN . 0 - 7o 0.20 M IN . 0.45 0.75 AL L D IM E N S IO N S IN M ILLIM E T ER S. 1.00 REF. 48-Pin Lead Detail Figure 14-9. 48-Pin TQFP Package (Detail View) Page 14-6 Chapter 14. EZ-USB Packaging EZ-USB TRM v1.
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EZ-USB v 1.9 Appendices Table of Contents Appendix A: 8051 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-1 A.1 A.2 A.3 A.4 A.5 A.6 Introduction ............................................................................................ A-1 8051 Features ......................................................................................... A-1 Performance Overview .......................................................................... A-2 Software Compatibility ........
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EZ-USB Registers Addr Name Description D7 D6 D5 D4 D3 D2 D1 D0 Endpoint 0-7 Data Buffers Notes CPU Access Codes: 7B40 OUT7BUF (64 bytes) d7 d6 d5 d4 d3 d2 d1 d0 RW = Read or Write, 7B80 IN7BUF (64 bytes) d7 d6 d5 d4 d3 d2 d1 d0 R, r = read-only, 7BC0 OUT6BUF (64 bytes) d7 d6 d5 d4 d3 d2 d1 d0 W, w = write-only 7C00 IN6BUF (64 bytes) d7 d6 d5 d4 d3 d2 d1 d0 b = both (Read & Write) 7C40 OUT5BUF (64 bytes) d7 d6 d5 d4 d3 d2 d1 d0 7C80 IN
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EZ-USB Registers Addr Name Description D7 D6 D5 D4 D3 D2 D1 D0 Endpoint 0-7 Data Buffers Notes CPU Access Codes: 7B40 OUT7BUF (64 bytes) d7 d6 d5 d4 d3 d2 d1 d0 RW = Read or Write, 7B80 IN7BUF (64 bytes) d7 d6 d5 d4 d3 d2 d1 d0 R, r = read-only, 7BC0 OUT6BUF (64 bytes) d7 d6 d5 d4 d3 d2 d1 d0 W, w = write-only 7C00 IN6BUF (64 bytes) d7 d6 d5 d4 d3 d2 d1 d0 b = both (Read & Write) 7C40 OUT5BUF (64 bytes) d7 d6 d5 d4 d3 d2 d1 d0 7C80 IN
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EZ-USB Registers Addr Name Description D7 D6 D5 D4 D3 D2 D1 D0 Notes Isochronous Byte Counts 7F70 OUT8BCH EP8 Out Byte Count H 0 0 0 0 0 0 d9 d8 7F71 OUT8BCL EP8 Out Byte Count L d7 d6 d5 d4 d3 d2 d1 d0 7F72 OUT9BCH EP9 Out Byte Count H 0 0 0 0 0 0 d9 d8 7F73 OUT9BCL EP9 Out Byte Count L d7 d6 d5 d4 d3 d2 d1 d0 7F74 OUT10BCH EP10 Out Byte Count H 0 0 0 0 0 0 d9 d8 7F75 OUT10BCL EP10 Out Byte Count L d7 d6 d5 d4 d3 d2 d1 d0 7F76
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EZ-USB Registers Addr Name Description D7 D6 D5 D4 D3 D2 D1 D0 Notes Interrupts 7FA8 IVEC Interrupt Vector 7FA9 IN07IRQ EPIN Interrupt Request 0 IV4 IV3 IV2 IV1 IV0 0 0 IN7IR IN6IR IN5IR IN4IR IN3IR IN2IR IN1IR IN0IR 7FAA OUT07IRQ EPOUT Interrupt Request 1=request OUT7IR OUT6IR OUT5IR OUT4IR OUT3IR OUT2IR OUT1IR OUT0IR 7FAB USBIRQ USB Interrupt Request 1=request * * IBNIR URESIR SUSPIR SUTOKIR SOFIR SUDAVIR 7FAC IN07IEN EP0-7IN Int Enables 1=requ
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EZ-USB Registers Addr Name Description D7 D6 D5 D4 D3 D2 D1 D0 A8 Notes Global USB Registers 7FD4 SUDPTRH Setup Data Ptr H A15 A14 A13 A12 A11 A10 A9 7FD5 SUDPTRL Setup Data Ptr L A7 A6 A5 A4 A3 A2 A1 A0 7FD6 USBCS USB Control & Status WakeSRC * * * DisCon DiscOE ReNum SIGRSUME 7FD7 TOGCTL Toggle Control Q S R IO 0 EP2 EP1 EP0 7FD8 USBFRAMEL Frame Number L FC7 FC6 FC5 FC4 FC3 FC2 FC1 FC0 7FD9 USBFRAMEH Frame Number H 0 0 0 0 0 FC10
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EZ-USB Registers Addr Name Description D7 D6 D5 D4 D3 D2 D1 D0 Notes Isochronous Byte Counts 7F70 OUT8BCH EP8 Out Byte Count H 0 0 0 0 0 0 d9 d8 7F71 OUT8BCL EP8 Out Byte Count L d7 d6 d5 d4 d3 d2 d1 d0 7F72 OUT9BCH EP9 Out Byte Count H 0 0 0 0 0 0 d9 d8 7F73 OUT9BCL EP9 Out Byte Count L d7 d6 d5 d4 d3 d2 d1 d0 7F74 OUT10BCH EP10 Out Byte Count H 0 0 0 0 0 0 d9 d8 7F75 OUT10BCL EP10 Out Byte Count L d7 d6 d5 d4 d3 d2 d1 d0 7F76
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EZ-USB Registers Addr Name Description D7 D6 D5 D4 D3 D2 D1 D0 Notes Interrupts 7FA8 IVEC Interrupt Vector 7FA9 IN07IRQ EPIN Interrupt Request 0 IV4 IV3 IV2 IV1 IV0 0 0 IN7IR IN6IR IN5IR IN4IR IN3IR IN2IR IN1IR IN0IR 7FAA OUT07IRQ EPOUT Interrupt Request 1=request OUT7IR OUT6IR OUT5IR OUT4IR OUT3IR OUT2IR OUT1IR OUT0IR 7FAB USBIRQ USB Interrupt Request 1=request * * IBNIR URESIR SUSPIR SUTOKIR SOFIR SUDAVIR 7FAC IN07IEN EP0-7IN Int Enables 1=requ
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EZ-USB Registers Addr Name Description D7 D6 D5 D4 D3 D2 D1 D0 A8 Notes Global USB Registers 7FD4 SUDPTRH Setup Data Ptr H A15 A14 A13 A12 A11 A10 A9 7FD5 SUDPTRL Setup Data Ptr L A7 A6 A5 A4 A3 A2 A1 A0 7FD6 USBCS USB Control & Status WakeSRC * * * DisCon DiscOE ReNum SIGRSUME 7FD7 TOGCTL Toggle Control Q S R IO 0 EP2 EP1 EP0 7FD8 USBFRAMEL Frame Number L FC7 FC6 FC5 FC4 FC3 FC2 FC1 FC0 7FD9 USBFRAMEH Frame Number H 0 0 0 0 0 FC10
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C.2.8 Timer 2 ..............................................................................................C-9 C.2.8.1 Timer 2 Mode Control .............................................................C-9 C.2.8.2 16-Bit Timer/Counter Mode ...................................................C-10 C.2.8.3 6-Bit Timer/Counter Mode with Capture ...............................C-11 C.2.8.4 16-Bit Timer/Counter Mode with Auto-Reload .....................C-12 C.2.8.5 Baud Rate Generator Mode ........................
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List of Figures Figure A-1. Figure B-1. Figure B-2 Figure B-3 Figure C-1. Figure C-2. Figure C-3. Figure C-4. Figure C-5. Figure C-6. Figure C-7. Figure C-8. Figure C-9. Figure C-10. Figure C-11. Figure C-12. Figure C-13. Figure C-14. Figure C-15. Figure C-16. Comparative Timing of 8051 and Industry Standard 8051 . . . . . . . . . . A-3 8051 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-1 Internal RAM Organization . . . . . . . . . . . . . . . . . . . . . .
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iv EZ-USB TRM v1.
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List of Tables Table A-1. Table B-1. Table B-2. Table B-3. Table B-4. Table B-5. Table B-6. Table C-1. Table C-2. Table C-3. Table C-4. Table C-5. Table C-6. Table C-7. Table C-8. Table C-9. Table C-10. Table C-11. Table C-12. Table C-13. Table C-14. Table C-15. Table C-16. Table C-17. Table C-18. Table C-19. Table C-20. v Feature Summary of 8051 Core and Common 803x/805x Configurations A-4 Legend for Instruction Set Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
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Appendix A: 8051 Introduction A.1 Introduction The EZ-USB contains an 8051 core that is binary compatible with the industry standard 8051 instruction set. This appendix provides an overview of the 8051 core features. the topics are: • New 8051 Features • Performance Overview • Software Compatibility • 803x/805x Feature Comparison • 8051/DS80C320 Differences A.
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A.3 Performance Overview The 8051 core has been designed to offer increased performance by executing instructions in a 4-clock bus cycle, as opposed to the 12-clock bus cycle in the standard 8051 (see Figure A-1.). The shortened bus timing improves the instruction execution rate for most instructions by a factor of three over the standard 8051 architectures. Some instructions require a different number of instruction cycles on the 8051 core than they do on the standard 8051.
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8051 Timing single byte single cycle instruction ALE PSEN# AD0-AD7 PORT2 4 XTAL1 12 ALE PSEN# AD0-AD7 PORT2 single byte single cycle instruction Standard 8051 Timing Figure A-1. Comparative Timing of 8051 and Industry Standard 8051 A.4 Software Compatibility The 8051 core is object code compatible with the industry standard 8051 micro-controller. That is, object code compiled with an industry standard 8051 compiler or assembler will execute on the 8051 core and will be functionally equivalent.
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A.5 803x/805x Feature Comparison Table A-1. provides a feature-by-feature comparison of the 8051 core and several common 803x/805x configurations. Table A-1.
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A.6 8051 Core/DS80C320 Differences The 8051 core is similar to the DS80C320 in terms of hardware features and instruction cycle timing. However, there are some important differences between the 8051 core and the DS80C320. A.6.1 Serial Ports The 8051 core does not implement serial port framing error detection and does not implement slave address comparison for multiprocessor communications. Therefore, the 8051 core also does not implement the following SFRs: SADDR0, SADDR1, SADEN0, and SADEN1. A.6.
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A-6 Appendix A: 8051 Introduction EZ-USB TRM v1.
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Appendix B: 8051 Architectural Overview B.1 Introduction This appendix provides a technical overview and description of the 8051 core architecture. PC4/TO, PC5/T1 8051 PA0/t0_out, PA1/t0_out 8051_cpu 8051_timer2 8051_timer 8051_ram_128 Timer 2 Timers 0 and 1 PB0/T2 PB1/t2ex PB7/t2out (80..FFh indirect) 8051_ram_128 (lower 128 Byte RAM) (0..
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B.1.1 Memory Organization Memory organization in the 8051 core is similar to that of the industry standard 8051. There are three distinct memory areas: program memory (ROM), data memory (external RAM), and registers (internal RAM). B.1.1.1 Program Memory The EZ-USB provides 8K of data that is mapped as both program and data memory at addresses 0x0000-0x1B3F. In addition, the bulk endpoint buffers may be used as external data memory if they are not used as endpoint buffers.
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B.1.2 Instruction Set All 8051 instructions are binary code compatible and perform the same functions as they do with the industry standard 8051. The effects of these instructions on bits, flags, and other status functions is identical to the industry standard 8051. However, the timing of the instructions is different, both in terms of number of clock cycles per instruction cycle and timing within the instruction cycle.
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Table B-1. Legend for Instruction Set Table Symbol B-4 Function A Accumulator Rn Register R7–R0 direct Internal register address @Ri Internal register pointed to by R0 or R1 (except MOVX) rel Two’s complement offset byte bit Direct bit address #data 8-bit constant #data 16 16-bit constant addr 16 16-bit destination address addr 11 11-bit destination address Appendix B: 8051 Architectural Overview EZ-USB TRM v1.
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Table B-2. 8051 Instruction Set Mnemonic Description Byte Instr.
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Table B-2. 8051 Instruction Set Mnemonic Description Byte Instr.
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Table B-2. 8051 Instruction Set Mnemonic Description Byte Instr.
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Table B-2. 8051 Instruction Set Mnemonic Description Byte Instr. Cycles Hex Code XCH A, @Ri Exchange A and data memory 1 1 C6-C7 XCHD A, @Ri Exchange A and data memory nibble 1 1 D6-D7 * Number of cycles is user-selectable. See “Stretch Memory Cycles (Wait States)” on page B-10.
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Table B-2. 8051 Instruction Set Mnemonic Description Byte Instr.
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accesses (bytes) needed to execute the instruction. In most cases, the number of bytes is equal to the number of instruction cycles required to complete the instruction. However, as indicated, there are some instructions (for example, DIV and MUL) that require a greater number of instruction cycles than memory accesses. By default, the 8051 core timer/counters run at 12 clock cycles per increment so that timerbased events have the same timing as with the standard 8051.
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By default, the stretch value resets to one (three cycle MOVX). For full-speed data memory access, the software must set the stretch value to zero. The stretch value affects only data memory access (not program memory). The stretch value affects the width of the read/write strobe and all related timing. Using a higher stretch value results in a wider read/write strobe, which allows the memory or peripheral more time to respond. Table B-3.
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All DPTR-related instructions use the currently selected data pointer. To switch the active pointer, toggle the SEL bit. The fastest way to do so is to use the increment instruction (INC DPS). This requires only one instruction to switch from a source address to a destination address, saving application code from having to save source and destination addresses when doing a block move. Using dual data pointers provides significantly increased efficiency when moving large blocks of data.
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Table B-4.
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Table B-4. Special Function Registers Register Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 TH2 Addr CDh PSW EICON(1) CY AC F0 RS1 RS0 OV F1 P D0h SMOD1 1 ERESI RESI INT6 0 0 0 D8h ACC E0H 1 EIE(1) 1 1 EWDI EX5 EX4 EI2C EUSB B E8h F0h 1 EIP(1) (1) 1 1 PX6 PX5 PX4 PI2C PUSB F8h Not part of standard 8051 architecture. Table B-5.
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Table B-5.
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Table B-6. PSW Register - SFR D0h B - 16 Bit Function PSW.7 CY - Carry flag. This is the unsigned carry bit. The CY flag is set when an arithmetic operation results in a carry from bit 7 to bit 8, and cleared otherwise. In other words, it acts as a virtual bit 8. The CY flag is cleared on multiplication and division. PSW.6 AC - Auxiliary carry flag.
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Appendix C: 8051 Hardware Description C.1 Introduction This chapter provides technical data about the 8051 core hardware operation and timing. The topics are: • Timers/Counters • Serial Interface • Interrupts • Reset • Power Saving Modes C.2 Timers/Counters The 8051 core includes three timer/counters (Timer 0, Timer 1, and Timer 2).
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C.2.1 803x/805x Compatibility The implementation of the timers/counters is similar to that of the Dallas Semiconductor DS80C320. Table C-1. summarizes the differences in timer/counter implementation between the Intel 8051, the Dallas Semiconductor DS80C320, and the 8051 core. Table C-1.
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The upper 3 bits of TL0 (or TL1) are indeterminate in mode 0 and must be masked when the software evaluates the register. Divide by 12 CLK24 T0M (or T1M) 0 1 0 CLK C/ T Divide by 4 0 TL0 (or TL1) 7 4 1 Mode 0 T0 (or T1) pin Mode 1 TR0 (or TR1) 0 TH0 (or TH1) 7 GATE INT0# pin (or INT1#) TF0 (or TF1) INT To Serial Port (Timer 1 only) Figure C-1. Timer 0/1 - Modes 0 and 1 C.2.4 Mode 1 Mode 1 operation is the same for Timer 0 and Timer 1. In mode 1, the timer is configured as a 16-bit counter.
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Table C-2. TMOD Register - SFR 89h C-4 Bit Function TMOD.7 GATE - Timer 1 gate control. When GATE = 1, Timer 1 will clock only when INT1# = 1 and TR1 (TCON.6) = 1. When GATE = 0, Timer 1 will clock only when TR1 = 1, regardless of the state of INT1#. TMOD.6 C/ T - Counter/Timer select. When C/ T = 0, Timer 1 is clocked by CLK24/4 or CLK24/12, depending on the state of T1M (CKCON.4). When C/ T = 1, Timer 1 is clocked by the T1 pin. TMOD.5 M1 - Timer 1 mode select bit 1. TMOD.
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Table C-3. TCON Register - SRF 88h EZ-USB TRM v1.9 Bit Function TCON.7 TF1 - Timer 1 overflow flag. Set to 1 when the Timer 1 count overflows and cleared when the processor vectors to the interrupt service routine. TCON.6 TR1 - Timer 1 run control. Set to 1 to enable counting on Timer 1. TCON.5 TF0 - Timer 0 overflow flag. Set to 1 when the Timer 0 count overflows and cleared when the processor vectors to the interrupt service routine. TCON.4 TR0 - Timer 0 run control.
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Divide by 12 T0M (or T1M) 0 CLK24 1 Divide by 4 C/ T 0 TL0 (or TL1) 0 7 RELOAD 1 CLK T0 (or T1) pin TR0 (or TR1) 0 TH0 (or TH1) 7 GATE TF0 (or TF1) INT0# pin (or INT1# pin) INT To Serial Port (Timer 1 only) Figure C-2. Timer 0/1 - Mode 2 C.2.5 Mode 2 Mode 2 operation is the same for Timer 0 and Timer 1. In mode 2, the timer is configured as an 8-bit counter, with automatic reload of the start value.
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Divide by 12 CLK24 T0M 0 1 Divide by 4 0 C/ T CLK 7 TL0 0 1 T0 pin TR0 TF0 INT TF1 INT GATE INT0# pin 0 TH0 7 TR1 Figure C-3. Timer 0 - Mode 3 C.2.6 Mode 3 In mode 3, Timer 0 operates as two 8-bit counters and Timer 1 stops counting and holds its value. As shown in Figure C-3., TL0 is configured as an 8-bit counter controlled by the normal Timer 0 control bits. TL0 can either count CLK24 cycles (divided by 4 or by 12) or high-tolow transitions on T0, as determined by the C/T bit.
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C.2.7 Timer Rate Control The default timer clock scheme for the 8051 timers is 12 CLK24 cycles per increment, the same as in the standard 8051. However, in the 8051, the instruction cycle is 4 CLK24 cycles. Using the default rate (12 clocks per timer increment) allows existing application code with real-time dependencies, such as baud rate, to operate properly.
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C.2.8 Timer 2 Timer 2 runs only in 16-bit mode and offers several capabilities not available with Timers 0 and 1. The modes available with Timer 2 are: • 16-bit timer/counter • 16-bit timer with capture • 16-bit auto-reload timer/counter • Baud rate generator The SFRs associated with Timer 2 are: • T2CON - SFR C8h (Table C-6.
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C.2.8.2 16-Bit Timer/Counter Mode Figure C-4. illustrates how Timer 2 operates in timer/counter mode with the optional capture feature. The C/T2 bit determines whether the 16-bit counter counts CLK24 cycles (divided by 4 or 12), or high-to-low transitions on the T2 pin. The TR2 bit enables the counter. When the count increments from FFFFh, the TF2 flag is set, and the T2OUT pin goes high for one CLK24 cycle. Table C-6. T2CON Register - SFR C8h C - 10 Bit Function T2CON.7 TF2 - Timer 2 overflow flag.
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Table C-6. T2CON Register - SFR C8h C.2.8.3 Bit Function T2CON.0 CP/RL2 - Capture/reload flag. When CP/RL2 = 1, Timer 2 captures occur on high-to-low transitions of the T2EX pin, if EXEN2 = 1. When CP/RL2 = 0, auto-reloads occur when Timer 2 overflows or when high-to-low transitions occur on the T2EX pin, if EXEN2 = 1. If either RCLK or TCLK is set to 1, CP/RL2 will not function and Timer 2 will operate in auto-reload mode following each overflow.
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C.2.8.4 16-Bit Timer/Counter Mode with Auto-Reload When CP/RL2 = 0, Timer 2 is configured for the auto-reload mode illustrated in Figure C-5.. Control of counter input is the same as for the other 16-bit counter modes. When the count increments from FFFFh, Timer 2 sets the TF2 flag and the starting value is reloaded into TL2 and TH2. The software must preload the starting value into the RCAP2L and RCAP2H registers.
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The counter time base in baud rate generator mode is CLK24/2. To use an external clock source, set C/T2 to 1 and apply the desired clock source to the T2 pin. TIMER 1 OVERFLOW CLK24 Divide by 2 0 C/ T2 Divide by 2 CLK 1 SMOD1 0 T2 pin TR2 7 8 0 TL2 15 RCLK TH2 0 1 1 RX CLOCK Divide by 16 TCLK RCAP2L EXEN2 T2EX pin 0 EXF2 RCAP2H 7 8 15 1 TIMER 2 INTERRUPT 0 Divide by 16 TX CLOCK Figure C-6. Timer 2 - Baud Rate Generator Mode C.
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Table C-7. Serial Port Modes Mode Sync/ Async 0 Sync CLK24/4 or CLK24/12 8 None None 1 Async Timer 1 or Timer 21 8 1 start, 1 stop None 2 Async CLK24/32 or CLK24/64 9 1 start, 1 stop 0, 1, parity 3 Async Timer 1 or Timer 21 9 1 start, 1 stop 0, 1, parity (1) Baud Clock Data Bits Start/Stop 9th Bit Function Timer 2 available for Serial Port 0 only. The SFRs associated with the serial ports are: • SCON0 - SFR 98h - Serial Port 0 control (Table C-8.).
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machine cycle after the 8th bit is shifted in, the RI_0 (or RI_1) bit is set and reception stops until the software clears the RI bit. Figure C-7.through Figure C-10.illustrate Serial Port Mode 0 transmit and receive timing for both low-speed (CLK24/12) and high-speed (CLK24/4) operation. Table C-8. SCON0 Register - SFR 98h Bit Function SCON0.7 SM0_0 - Serial Port 0 mode bit 0. SCON0.6 SM1_0 - Serial Port 0 mode bit 1, decoded as: SM0_0 0 0 1 1 SCON0.
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Table C-9. SCON1 Register - SFR C0h Bit Function SCON1.7 SM0_1 - Serial Port 1 mode bit 0. SCON1.6 SM1_1 - Serial Port 1 mode bit 1, decoded as: SM0_1 0 0 1 1 SCON1.5 SM1_1 0 1 0 1 Mode 0 1 2 3 SM2_1 - Multiprocessor communication enable. In modes 2 and 3, this bit enables the multiprocessor communication feature. If SM2_1 = 1 in mode 2 or 3, then RI_1 will not be activated if the received 9th bit is 0. If SM2_1=1 in mode 1, then RI_1 will only be activated if a valid stop is received.
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CLK24 PSEN D0 RXD0 D1 D2 D3 D4 D5 D6 D7 RXD0OUT TXD0 TI RI Figure C-7. Serial Port Mode 0 Receive Timing - Low Speed Operation CLK24 PSEN D0 RXD0 D1 D2 D3 D4 D5 D6 D7 RXD0OUT TXD0 TI RI Figure C-8. Serial Port Mode 0 Receive Timing - High Speed Operation EZ-USB TRM v1.
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CLK24 PSEN RXD0 RXD0OUT D0 D1 D2 D3 D4 D5 D6 D7 TXD0 TI RI Figure C-9. Serial Port Mode 0 Transmit Timing - Low Speed Operation CLK24 PSEN RXD0 RXD0OUT D0 D1 D2 D3 D4 D5 D6 D7 TXD0 TI RI Figure C-10. Serial Port Mode 0 Transmit Timing - High Speed Operation C - 18 Appendix C: 8051 Hardware Description EZ-USB TRM v1.
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C.3.3 Mode 1 Mode 1 provides standard asynchronous, full-duplex communication, using a total of 10 bits: 1 start bit, 8 data bits, and 1 stop bit. For receive operations, the stop bit is stored in RB8_0 (or RB8_1). Data bits are received and transmitted LSB first. C.3.3.1 Mode 1 Baud Rate The mode 1 baud rate is a function of timer overflow. Serial Port 0 can use either Timer 1 or Timer 2 to generate baud rates. Serial Port 1 can only use Timer 1.
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The 12 in the denominator in the above equation can be changed to 4 by setting the T1M bit in the CKCON SFR. To derive the required TH1 value from a known baud rate (when TM1 = 0), use the equation: TH1 = 256 - SMODx 2 x CLK24 384 x Baud Rate You can also achieve very low serial port baud rates from Timer 1 by enabling the Timer 1 interrupt, configuring Timer 1 to mode 1, and using the Timer 1 interrupt to initiate a 16-bit software reload. Table C-10.
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CLK24 Baud Rate = 32 x (65536 - RCAP2H,RCAP2L) where RCAP2H,RCAP2L is the content of RCAP2H and RCAP2L taken as a 16-bit unsigned number. The 32 in the denominator is the result of CLK24 being divided by 2 and the Timer 2 overflow being divided by 16. Setting TCLK or RCLK to 1 automatically causes CLK24 to be divided by 2, as shown in Figure C-6., instead of the 4 or 12 determined by the T2M bit in the CKCON SFR.
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C.3.3.2 Mode 1 Transmit Figure C-11. illustrates the mode 1 transmit timing. In mode 1, the UART begins transmitting after the first roll over of the divide-by-16 counter after the software writes to the SBUF0 (or SBUF1) register. The UART transmits data on the TXD0 (or TXD1) pin in the following order: start bit, 8 data bits (LSB first), stop bit. The TI_0 (or TI_1) bit is set 2 CLK24 cycles after the stop bit is transmitted. C.3.3.3 Mode 1 Receive Figure C-12. illustrates the mode 1 receive timing.
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Write to SBUF0 TX CLK SHIFT TXD0 START D0 D1 D2 D3 D4 D5 D6 D7 STOP RXD0 RXD0OUT TI_0 RI_0 Figure C-11. Serial Port 0 Mode 1 Transmit Timing RX CLK RXD0 START D0 D1 D2 D3 D4 D5 D6 D7 STOP Bit detector sampling SHIFT RXD0OUT TXD0 TI_0 RI_0 Figure C-12. Serial Port 0 Mode 1 Receive Timing EZ-USB TRM v1.
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C.3.4 Mode 2 Mode 2 provides asynchronous, full-duplex communication, using a total of 11 bits: 1 start bit, 8 data bits, a programmable 9th bit, and 1 stop bit. The data bits are transmitted and received LSB first. For transmission, the 9th bit is determined by the value in TB8_0 (or TB8_1). To use the 9th bit as a parity bit, move the value of the P bit (SFR PSW.0) to TB8_0 (or TB8_1). The mode 2 baud rate is either CLK24/32 or CLK24/64, as determined by the SMOD0 (or SMOD1) bit.
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If the above conditions are met, the serial port then writes the received byte to the SBUF0 (or SBUF1) register, loads the stop bit into RB8_0 (or RB8_1), and sets the RI_0 (or RI_1) bit. If the above conditions are not met, the received data is lost, the SBUF register and RB8 bit are not loaded, and the RI bit is not set. After the middle of the stop bit time, the serial port waits for another high-to-low transition on the RXD0 (or RXD1) pin.
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C.3.5 Mode 3 Mode 3 provides asynchronous, full-duplex communication, using a total of 11 bits: 1 start bit, 8 data bits, a programmable 9th bit, and 1 stop bit. The data bits are transmitted and received LSB first. The mode 3 transmit and operations are identical to mode 2. The mode 3 baud rate generation is identical to mode 1. That is, mode 3 is a combination of mode 2 protocol and mode 1 baud rate. Figure C-15.illustrates the mode 3 transmit timing. Figure C-16.illustrates the mode 3 receive timing.
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C.3.6 Multiprocessor Communications The multiprocessor communication feature is enabled in modes 2 and 3 when the SM2 bit is set in the SCON SFR for a serial port (SM2_0 for Serial Port 0, SM2_1 for Serial Port 1). In multiprocessor communication mode, the 9th bit received is stored in RB8_0 (or RB8_1) and, after the stop bit is received, the serial port interrupt is activated only if RB8_0 (or RB8_1) = 1.
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Table C-12. IE Register - SFR A8h C - 28 Bit Function IE.7 EA - Global interrupt enable. Controls masking of all interrupts except USB wakeup (resume). EA = 0 disables all interrupts except USB wakeup. When EA = 1, interrupts are enabled or masked by their individual enable bits. IE.6 ES1 - Enable Serial Port 1 interrupt. ES1 = 0 disables Serial port 1 interrupts (TI_1 and RI_1). ES1 = 1 enables interrupts generated by the TI_1 or TI_1 flag. IE.5 ET2 - Enable Timer 2 interrupt.
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Table C-13. IP Register - SFR B8h Bit EZ-USB TRM v1.9 Function IP.7 Reserved. Read as 1. IP.6 PS1 - Serial Port 1 interrupt priority control. PS1=0 sets Serial Port 1 interrupt (TI_1 or RI_1) to low priority. PS1=1 sets Serial port 1 interrupt to high priority. IP.5 PT2 - Timer 2 interrupt priority control. PT2=0 sets Timer 2 interrupt (TF2) to low priority. PT2=1 sets Timer 2 interrupt to high priority. IP.4 PS0 - Serial Port 0 interrupt priority control.
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Table C-14. EXIF Register - SFR 91h C - 30 Bit Function EXIF.7 IE5 - External interrupt 5 flag. IE 5= 1 indicates a falling edge was detected at the INT5# pin. IE5 must be cleared by software. Setting IE5 in software generates an interrupt, if enabled. EXIF.6 IE4 - External interrupt 4 flag. IE4 indicates a rising edge was detected at the INT4 pin. IE4 must be cleared by software. Setting IE4 in software generates an interrupt, if enabled. EXIF.5 I2CINT - External interrupt 3 flag.
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Table C-15. EICON Register - SFR D8h Bit EICON.7 SMOD1 - Serial Port 1 baud rate doubler enable. When SMOD1 = 1 the baud rate for Serial Port is doubled. EICON.6 Reserved. Read as 1. EICON.5 ERESI - Enable resume interrupt. ERESI = 0 disables resume interrupt (RESI). ERESI = 1 enables interrupts generated by the resume event. EICON.4 RESI - Wakeup interrupt flag. EICON.4 = 1 indicates a negative transition was detected at the WAKEUP# pin, or that USB has activity resumed from the suspended state.
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Table C-16. EIE Register - SFR E8h Bit EIE.7-5 C - 32 Function Reserved. Read as 1. EIE.4 EX6 - Enable external interrupt 6. EX6 = 0 disables external interrupt 6 (INT6). EX6 = 1 enables interrupts generated by the INT6 pin. EIE.3 EX5 - Enable external interrupt 5. EX5 = 0 disables external interrupt 5 (INT5). EX5 = 1 enables interrupts generated by the INT5# pin. EIE.2 EX4 - Enable external interrupt 4. EX4 = 0 disables external interrupt 4 (INT4).
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Table C-17. EIP Register - SFR F8h Bit Function EIP.7-5 C.4 Reserved. Read as 1. EIP.4 PX6 - External interrupt 6 priority control. PX6 = 0 sets external interrupt 6 (INT6) to low priority. PX6 = 1 sets external interrupt 6 to high priority. EIP.3 PX5 - External interrupt 5 priority control. PX5 = 0 sets external interrupt 5 (INT5#) to low priority. PX5=1 sets external interrupt 5 to high priority. EIP.2 PX4 - External interrupt 4 priority control.
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Table C-19. provides a summary of interrupt sources, flags, enables, and priorities. Table C-18.
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Table C-19. Interrupt Flags, Enables, and Priority Control Interrupt Description Enable Priority Control EICON.5 N/A Flag RESUME Resume interrupt EICON.4 INT0 External interrupt 0 TCON.1 IE.0 IP.0 TF0 Timer 0 interrupt TCON.5 IE.1 IP.1 INT1 External interrupt 1 TCON.3 IE.2 IP.2 TF1 Timer 1 interrupt TCON.7 IE.3 IP.3 TI_0 or RI_0 Serial port 0 transmit or receive SCON0.0 (RI.0), SCON0.1 (Ti_0) IE.4 IP.4 TF2 or EXF2 Timer 2 interrupt T2CON.7 (TF2), T2CON.6 (EXF2) IE.5 IP.
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latched and must remain active until serviced. C.4.4 Interrupt Latency Interrupt response time depends on the current state of the 8051. The fastest response time is 5 instruction cycles: 1 to detect the interrupt, and 4 to perform the LCALL to the ISR. The maximum latency (13 instruction cycles) occurs when the 8051 is currently executing a RETI instruction followed by a MUL or DIV instruction.
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mode and shuts down the 24 MHz oscillator. See Chapter 11, "EZ-USB Power Management" for a full description of the Suspend/Resume process. Table C-20. PCON Register - SFR 87h Bit PCON.7 PCON.6-4 EZ-USB TRM v1.9 Function SMOD0 - Serial Port 0 baud rate double enable. When SMOD0 = 1, the baud rate for Serial Port 0 is doubled. Reserved. PCON.3 GF1 - General purpose flag 1. Bit-addressable, general purpose flag for software control. PCON.2 GF0 - General purpose flag 0.
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C - 38 Appendix C: 8051 Hardware Description EZ-USB TRM v1.