Synchronous Dual-Port RAM Specification Sheet

ManualsBrandsCypress ManualsComputer HardwareFLEx18 CY7C0832AV

FLEx18™ 3.3V 64K/128K x 36 and

128K/256K x 18 Synchronous Dual-Port RAM

CY7C0837AV, CY7C0830AV

CY7C0831AV, CY7C0832AV

CY7C0832BV, CY7C0833AV

Cypress Semiconductor Corporation • 198 Champion Court • San Jose

CA 95134-1709 • 408-943-2600

Document #: 38-06059 Rev. *S Revised March 03, 2009

Features

■

True Dual-Ported Memory Cells that Allow Simultaneous

Access of the Same Memory Location

■

Synchronous Pipelined Operation

■

Family of 512 Kbit, 1 Mbit, 2 Mbit, 4 Mbit, and 9 Mbit Devices

■

Pipelined Output Mode Allows Fast Operation

■

0.18 micron CMOS for Optimum Speed and Power

■

High Speed Clock to Data Access

■

3.3V Low Power

❐

Active as Low as 225 mA (typ)

❐

Standby as Low as 55 mA (typ)

■

Mailbox Function for Message Passing

■

Global Master Reset

■

Separate Byte Enables on Both Ports

■

Commercial and Industrial Temperature Ranges

■

IEEE 1149.1 Compatible JTAG Boundary Scan

■

144-Ball FBGA (13 mm × 13 mm) (1.0 mm pitch)

■

120 TQFP (14 mm x 14 mm x 1.4 mm)

■

Pb-Free Packages Available

■

Counter Wrap Around Control

❐

Internal Mask Register Controls Counter Wrap Around

❐

Counter-Interrupt Flags to Indicate Wrap Around

❐

Memory Block Retransmit Operation

■

Counter Readback on Address Lines

■

Mask Register Readback on Address Lines

■

Dual Chip Enables on Both Ports for Easy Depth Expansion

Functional Description

The FLEx18™ family includes 512 Kbit, 1 Mbit, 2 Mbit, 4 Mbit,

and 9 Mbit pipelined, synchronous, true dual port static RAMs

that are high speed, low power 3.3V CMOS. Two ports are

provided, permitting independent, simultaneous access to any

location in memory. The result of writing to the same location by

more than one port at the same time is undefined. Registers on

control, address, and data lines allow for minimal setup and hold

time.

During a Read operation, data is registered for decreased cycle

time. Each port contains a burst counter on the input address

address, the counter increments the address internally (more

details to follow). The internal Write pulse width is independent

of the duration of the R/W

input signal. The internal Write pulse

is self-timed to allow the shortest possible cycle times.

A HIGH on CE0

or LOW on CE1 for one clock cycle powers down

the internal circuitry to reduce the static power consumption. One

cycle with chip enables asserted is required to reactivate the

outputs.

Additional features include: readback of burst-counter internal

address value on address lines, counter-mask registers to

control the counter wrap around, counter interrupt (CNTINT

)

flags, readback of mask register value on address lines,

retransmit functionality, interrupt flags for message passing,

JTAG for boundary scan, and asynchronous Master Reset

(MRST

The CY7C0833AV device in this family has limited features. See

Address Counter and Mask Register Operations

[16]

on page 6

for details.

Table 1. Product Selection Guide

Density

512 Kbit

(32K x 18)

1 Mbit

(64K x 18)

2 Mbit

(128K x 18)

4 Mbit

(256K x 18)

9 Mbit

(512K x 18)

Part Number CY7C0837AV CY7C0830AV CY7C0831AV CY7C0832AV CY7C0832BV

[1]

CY7C0833AV

Maximum Speed (MHz) 167 167 167 167 133 133

Maximum Access Time -

Clock to Data (ns)

4.0 4.0 4.0 4.0 4.4 4.7

Typical Operating

Current (mA)

225 225 225 225 225 270

Package 144 FBGA 120 TQFP

144 FBGA

120 TQFP

144 FBGA

120 TQFP

144 FBGA

120 TQFP 144 FBGA

Note

1. CY7C0832AV and CY7C0832BV are functionally identical.

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Summary of content (28 pages)

PAGE 1
CY7C0837AV, CY7C0830AV CY7C0831AV, CY7C0832AV CY7C0832BV, CY7C0833AV FLEx18™ 3.3V 64K/128K x 36 and 128K/256K x 18 Synchronous Dual-Port RAM Features Functional Description ■ True Dual-Ported Memory Cells that Allow Simultaneous Access of the Same Memory Location ■ Synchronous Pipelined Operation ■ Family of 512 Kbit, 1 Mbit, 2 Mbit, 4 Mbit, and 9 Mbit Devices ■ Pipelined Output Mode Allows Fast Operation ■ 0.
PAGE 2
CY7C0837AV, CY7C0830AV CY7C0831AV, CY7C0832AV CY7C0832BV, CY7C0833AV Logic Block Diagram [2] OEL R/WL OER R/WR B0L B0R B1L B1R CE0L CE1L DQ9L–DQ17L DQ0L–DQ8L CE0R CE1R I/O Control 9 I/O Control 9 9 9 Addr. Read Back DQ9R–DQ17R DQ0R–DQ8R Addr.
PAGE 3
CY7C0837AV, CY7C0830AV CY7C0831AV, CY7C0832AV CY7C0832BV, CY7C0833AV Pin Configurations Figure 1.
PAGE 4
CY7C0837AV, CY7C0830AV CY7C0831AV, CY7C0832AV CY7C0832BV, CY7C0833AV Pin Configurations Figure 2.
PAGE 5
CY7C0837AV, CY7C0830AV CY7C0831AV, CY7C0832AV CY7C0832BV, CY7C0833AV Pin Definitions Left Port Right Port Description A0L–A18L[2] A0R–A18R[2] Address Inputs. ADSL[8] ADSR[8] Address Strobe Input. Used as an address qualifier. This signal should be asserted LOW for the part using the externally supplied address on the address pins and for loading this address into the burst address counter. CE0L[8] CE0R[8] Active LOW Chip Enable Input. CE1L[7] CE1R [7] Active HIGH Chip Enable Input.
PAGE 6
CY7C0837AV, CY7C0830AV CY7C0831AV, CY7C0832AV CY7C0832BV, CY7C0833AV Master Reset The counter register contains the address used to access the RAM array. It is changed only by the Counter Load, Increment, Counter Reset, and by master reset (MRST) operations. The FLEx18 family devices undergo a complete reset by taking its MRST input LOW. The MRST input can switch asynchronously to the clocks.
PAGE 7
CY7C0837AV, CY7C0830AV CY7C0831AV, CY7C0832AV CY7C0832BV, CY7C0833AV Counter Reset Operation All unmasked bits of the counter are reset to ‘0.’ All masked bits remain unchanged. The mirror register is loaded with the value of the burst counter. A Mask Reset followed by a Counter Reset resets the counter and mirror registers to 00000, as does master reset (MRST). Counter Load Operation The address counter and mirror registers are both loaded with the address value presented at the address lines.
PAGE 8
CY7C0837AV, CY7C0830AV CY7C0831AV, CY7C0832AV CY7C0832BV, CY7C0833AV Retransmit Mask Readback Operation Retransmit is a feature that allows the Read of a block of memory more than once without the need to reload the initial address. This eliminates the need for external logic to store and route data. It also reduces the complexity of the system design and saves board space. An internal mirror register is used to store the initially loaded address counter value.
PAGE 9
CY7C0837AV, CY7C0830AV CY7C0831AV, CY7C0832AV CY7C0832BV, CY7C0833AV Figure 3.
PAGE 10
CY7C0837AV, CY7C0830AV CY7C0831AV, CY7C0832AV CY7C0832BV, CY7C0833AV Figure 4.
PAGE 11
CY7C0837AV, CY7C0830AV CY7C0831AV, CY7C0832AV CY7C0832BV, CY7C0833AV Figure 5. Scan Chain for 9 Mb Device TDO TDO D2 TDI TDO D1 TDI TDI Table 4. Identification Register Definitions Instruction Field Value Description Revision Number (31:28) 0h Cypress Device ID (27:12) C090h Reserved for version number.
PAGE 12
CY7C0837AV, CY7C0830AV CY7C0831AV, CY7C0832AV CY7C0832BV, CY7C0833AV Maximum Ratings Output Current into Outputs (LOW)............................. 20 mA Exceeding maximum ratings[23] may impair the useful life of the device. These user guidelines are not tested. Static Discharge Voltage........................................... > 2000V (JEDEC JESD22-A114-2000B) Storage Temperature ................................. –65°C to +150°C Latch Up Current ....................................................
PAGE 13
CY7C0837AV, CY7C0830AV CY7C0831AV, CY7C0832AV CY7C0832BV, CY7C0833AV Figure 6. AC Test Load and Waveforms 3.3V Z0 = 50Ω R = 50Ω R1 = 590 Ω OUTPUT OUTPUT C = 10 pF C = 5 pF VTH = 1.5V (a) Normal Load (Load 1) R2 = 435 Ω (b) Three-state Delay (Load 2) 3.
PAGE 14
CY7C0837AV, CY7C0830AV CY7C0831AV, CY7C0832AV CY7C0832BV, CY7C0833AV Switching Characteristics (continued) Over the Operating Range -167 Parameter Description tHCM CNT/MSK Hold Time Output Enable to Data Valid tOE OE to Low Z tOLZ[28,29] tOHZ[28,29] OE to High Z Clock to Data Valid tCD2 Clock to Counter Address Valid tCA2 tCM2 Clock to Mask Register Readback Valid tDC Data Output Hold After Clock HIGH tCKHZ[28,29] Clock HIGH to Output High Z tCKLZ[28, 29] Clock HIGH to Output Low Z tSINT Clock to INT S
PAGE 15
CY7C0837AV, CY7C0830AV CY7C0831AV, CY7C0832AV CY7C0832BV, CY7C0833AV JTAG Timing and Switching Waveforms Parameter CY7C0837AV/CY7C0830AV CY7C0831AV/CY7C0832AV CY7C0832BV/CY7C0833AV Description Min Unit Max fJTAG Maximum JTAG TAP Controller Frequency tTCYC TCK Clock Cycle Time 100 tTH TCK Clock HIGH Time 40 ns tTL TCK Clock LOW Time 40 ns tTMSS TMS Setup to TCK Clock Rise 10 ns tTMSH TMS Hold After TCK Clock Rise 10 ns tTDIS TDI Setup to TCK Clock Rise 10 ns tTDIH TDI Hold Aft
PAGE 16
CY7C0837AV, CY7C0830AV CY7C0831AV, CY7C0832AV CY7C0832BV, CY7C0833AV Switching Waveforms Figure 8. Master Reset tRS MRST ALL ADDRESS/ DATA LINES tRSF tRSS ALL OTHER INPUTS tRSR INACTIVE ACTIVE TMS CNTINT INT TDO Figure 9. Read Cycle[12, 30, 31, 32, 33] tCH2 tCYC2 tCL2 CLK CE tSC tHC tSB tHB tSW tSA tHW tHA tSC tHC BE0–BE1 R/W ADDRESS An DATAOUT An+1 1 Latency An+2 tDC tCD2 Qn tCKLZ An+3 Qn+1 tOHZ Qn+2 tOLZ OE tOE Notes 30.
PAGE 17
CY7C0837AV, CY7C0830AV CY7C0831AV, CY7C0832AV CY7C0832BV, CY7C0833AV Switching Waveforms (continued) Figure 10. Bank Select Read[34, 35] tCH2 tCYC2 tCL2 CLK tHA tSA ADDRESS(B1) A0 A1 A3 A2 A4 A5 tHC tSC CE(B1) tCD2 tHC tSC tCD2 tHA tSA tDC A0 ADDRESS(B2) A1 tCKHZ Q3 Q1 Q0 DATAOUT(B1) tCD2 tCKHZ tDC tCKLZ A3 A2 A4 A5 tHC tSC CE(B2) tSC tCD2 tHC DATAOUT(B2) tCKHZ tCD2 Q4 Q2 tCKLZ tCKLZ Figure 11.
PAGE 18
CY7C0837AV, CY7C0830AV CY7C0831AV, CY7C0832AV CY7C0832BV, CY7C0833AV Switching Waveforms (continued) Figure 12. Read-to-Write-to-Read (OE Controlled)[33, 36, 38, 39] tCH2 tCYC2 tCL2 CLK CE tSC tHC tSW tHW R/W tSW tHW An An+1 An+2 An+3 An+4 An+5 ADDRESS tSA tHA tSD tHD Dn+2 DATAIN Dn+3 tCD2 DATAOUT tCD2 Qn Qn+4 tOHZ OE READ WRITE READ Figure 13.
PAGE 19
CY7C0837AV, CY7C0830AV CY7C0831AV, CY7C0832AV CY7C0832BV, CY7C0833AV Switching Waveforms (continued) Figure 14. Write with Address Counter Advance[39] tCH2 tCYC2 tCL2 CLK tSA tHA An ADDRESS INTERNAL ADDRESS An tSAD tHAD tSCN tHCN An+1 An+2 An+3 An+4 ADS CNTEN Dn DATAIN tSD Dn+1 tHD WRITE EXTERNAL ADDRESS Dn+1 WRITE WITH COUNTER Dn+2 Dn+3 WRITE COUNTER HOLD Figure 15.
PAGE 20
CY7C0837AV, CY7C0830AV CY7C0831AV, CY7C0832AV CY7C0832BV, CY7C0833AV Switching Waveforms (continued) Figure 16. Readback State of Address Counter or Mask Register[43, 44, 45, 46] tCYC2 tCH2 tCL2 CLK tCA2 or tCM2 tSA tHA EXTERNAL ADDRESS A0–A16 An* An INTERNAL ADDRESS An+1 An An+2 An+4 An+3 tSAD tHAD ADS tSCN tHCN CNTEN tCD2 DATAOUT Qx-2 LOAD EXTERNAL ADDRESS tCKHZ Qx-1 Qn READBACK COUNTER INTERNAL ADDRESS INCREMENT tCKLZ Qn+1 Qn+2 Qn+3 Notes 43.
PAGE 21
CY7C0837AV, CY7C0830AV CY7C0831AV, CY7C0832AV CY7C0832BV, CY7C0833AV Switching Waveforms (continued) Figure 17. Left_Port (L_Port) Write to Right_Port (R_Port) Read[47, 48, 49] tCH2 tCYC2 tCL2 CLKL tHA tSA L_PORT ADDRESS An tSW tHW R/WL tCKHZ tSD L_PORT DATAIN CLKR tHD tCKLZ Dn tCYC2 tCL2 tCCS tCH2 tSA R_PORT ADDRESS tHA An R/WR tCD2 R_PORT Qn DATAOUT tDC Notes 47. CE0 = OE = ADS = CNTEN = BE0 – BE1 = LOW; CE1 = CNTRST = MRST = CNT/MSK = HIGH. 48.
PAGE 22
CY7C0837AV, CY7C0830AV CY7C0831AV, CY7C0832AV CY7C0832BV, CY7C0833AV Switching Waveforms (continued) Figure 18. Counter Interrupt and Retransmit [15, 42, 50, 51, 52, 53] tCH2 tCYC2 tCL2 CLK tSCM tHCM CNT/MSK ADS CNTEN COUNTER INTERNAL ADDRESS 3FFFC 3FFFD 3FFFE tSCINT 3FFFF Last_Loaded Last_Loaded +1 tRCINT CNTINT Notes 50. CE0 = OE = BE0 – BE1 = LOW; CE1 = R/W = CNTRST = MRST = HIGH. 51. CNTINT is always driven. 52.
PAGE 23
CY7C0837AV, CY7C0830AV CY7C0831AV, CY7C0832AV CY7C0832BV, CY7C0833AV Switching Waveforms (continued) Figure 19. MailBox Interrupt Timing [54, 55, 56, 57, 58] tCH2 tCYC2 tCL2 CLKL tSA L_PORT ADDRESS tHA 7FFFF An+1 An An+2 An+3 tSINT tRINT INTR tCH2 tCYC2 tCL2 CLKR tSA R_PORT ADDRESS tHA Am+1 Am 7FFFF Am+3 Am+4 Table 7.
PAGE 24
CY7C0837AV, CY7C0830AV CY7C0831AV, CY7C0832AV CY7C0832BV, CY7C0833AV Ordering Information 512K × 18 (9M) 3.3V Synchronous CY7C0833AV Dual-Port SRAM Speed (MHz) 133 100 Ordering Code Package Diagram Package Type Operating Range CY7C0833AV-133BBC 51-85141 144-Ball Grid Array (13 x 13 x 1.6 mm) with 1 mm pitch Commercial CY7C0833AV-133BBI 51-85141 144-Ball Grid Array (13 x 13 x 1.6 mm) with 1 mm pitch Industrial CY7C0833AV-100BBC 51-85141 144-Ball Grid Array (13 x 13 x 1.
PAGE 25
CY7C0837AV, CY7C0830AV CY7C0831AV, CY7C0832AV CY7C0832BV, CY7C0833AV Ordering Information 32K × 18 (512K) 3.3V Synchronous CY7C0837AV Dual-Port SRAM Speed (MHz) Ordering Code Package Diagram Operating Range Package Type 167 CY7C0837AV-167BBC 51-85141 144-Ball Grid Array (13 x 13 x 1.6 mm) with 1 mm pitch Commercial 133 CY7C0837AV-133BBC 51-85141 144-Ball Grid Array (13 x 13 x 1.6 mm) with 1 mm pitch Commercial CY7C0837AV-133BBI 51-85141 144-Ball Grid Array (13 x 13 x 1.
PAGE 26
CY7C0837AV, CY7C0830AV CY7C0831AV, CY7C0832AV CY7C0832BV, CY7C0833AV Package Diagrams Figure 21. 120-Pin Thin Quad Flatpack (14 x 14 x 1.4 mm) (51-85100) 51-85100-** Document #: 38-06059 Rev.
PAGE 27
CY7C0837AV, CY7C0830AV CY7C0831AV, CY7C0832AV CY7C0832BV, CY7C0833AV Document History Page Document Title: CY7C0837AV/CY7C0830AV/CY7C0831AV/CY7C0832AV/CY7C0832BV/CY7C0833AV, FLEx18™ 3.3V 64K/128K x 36 and 128K/256K x 18 Synchronous Dual-Port RAM Document Number: 38-06059 Rev. ECN No. Orig.
PAGE 28
CY7C0837AV, CY7C0830AV CY7C0831AV, CY7C0832AV CY7C0832BV, CY7C0833AV Sales, Solutions, and Legal Information Worldwide Sales and Design Support Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office closest to you, visit us at cypress.com/sales. Products PSoC Clocks & Buffers PSoC Solutions psoc.cypress.com clocks.cypress.com General Low Power/Low Voltage psoc.cypress.com/solutions psoc.cypress.