Synchronous Dual-Port RAM Specification Sheet

CY7C0837AV, CY7C0830AV
CY7C0831AV, CY7C0832AV
CY7C0832BV, CY7C0833AV
Document #: 38-06059 Rev. *S Page 14 of 28
t
HCM
CNT/MSK Hold Time 0.6 0.6 NA NA ns
t
OE
Output Enable to Data Valid 4.0 4.4 4.7 5.0 ns
t
OLZ
[28,29]
OE to Low Z 0 0 ns
t
OHZ
[28,29]
OE to High Z 0 4.0 0 4.4 4.7 5.0 ns
t
CD2
Clock to Data Valid 4.0 4.4 4.7 5.0 ns
t
CA2
Clock to Counter Address Valid 4.0 4.4 NA NA ns
t
CM2
Clock to Mask Register Readback Valid 4.0 4.4 NA NA ns
t
DC
Data Output Hold After Clock HIGH 1.0 1.0 1.0 1.0 ns
t
CKHZ
[28,29]
Clock HIGH to Output High Z 0 4.0 0 4.4 4.7 5.0 ns
t
CKLZ
[28, 29]
Clock HIGH to Output Low Z 1.0 4.0 1.0 4.4 1.0 4.7 1.0 5.0 ns
t
SINT
Clock to INT Set Time 0.5 6.7 0.5 7.5 0.5 7.5 0.5 10 ns
t
RINT
Clock to INT Reset Time 0.5 6.7 0.5 7.5 0.5 7.5 0.5 10 ns
t
SCINT
Clock to CNTINT Set Time 0.5 5.0 0.5 5.7 NA NA NA NA ns
t
RCINT
Clock to CNTINT Reset time 0.5 5.0 0.5 5.7 NA NA NA NA ns
Port to Port Delays
t
CCS
Clock to Clock Skew 5.2 6.0 6.0 8.0 ns
Master Reset Timing
t
RS
Master Reset Pulse Width 7.0 7.5 7.5 10 ns
t
RS
Master Reset Setup Time 6.0 6.0 6.0 8.5 ns
t
RSR
Master Reset Recovery Time 6.0 7.5 7.5 10 ns
t
RSF
Master Reset to Outputs Inactive 10.0 10.0 10.0 10.0 ns
t
RSCNTINT
Master Reset to Counter Interrupt Flag
Reset Time
10.0 10.0 NA NA ns
Switching Characteristics (continued)
Over the Operating Range
Parameter Description
-167 -133 -100
Unit
CY7C0837AV
CY7C0830AV
CY7C0831AV
CY7C0832AV
CY7C0837AV
CY7C0830AV
CY7C0831AV
CY7C0832AV
CY7C0832BV
CY7C0833AV CY7C0833AV
Min Max Min Max Min Max Min Max
Notes
28. This parameter is guaranteed by design, but is not production tested.
29. Test conditions used are Load 2.
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