Synchronous Dual-Port RAM Specification Sheet

CY7C0837AV, CY7C0830AV
CY7C0831AV, CY7C0832AV
CY7C0832BV, CY7C0833AV
Document #: 38-06059 Rev. *S Page 18 of 28
Figure 12. Read-to-Write-to-Read (OE
Controlled)
[33, 36, 38, 39]
Figure 13. Read with Address Counter Advance
[38]
Switching Waveforms (continued)
t
CYC2
t
CL2
t
CH2
t
HC
t
SC
t
HW
t
SW
t
HA
t
SA
A
n
A
n+1
A
n+2
A
n+3
A
n+4
A
n+5
t
HW
t
SW
t
SD
t
HD
D
n+2
t
CD2
t
OHZ
READ READWRITE
D
n+3
Q
n
CLK
CE
R/W
ADDRESS
DATA
IN
DATA
OUT
OE
Q
n+4
t
CD2
t
SA
t
HA
t
CH2
t
CL2
t
CYC2
CLK
ADDRESS
A
n
COUNTER HOLD
READ WITH COUNTER
t
SAD
t
HAD
t
SCN
t
HCN
t
SAD
t
HAD
t
SCN
t
HCN
Q
x–1
Q
x
Q
n
Q
n+1
Q
n+2
Q
n+3
t
DC
t
CD2
READ WITH COUNTER
READ
EXTERNAL
ADDRESS
ADS
CNTEN
DATA
OUT
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