Synchronous Dual-Port RAM Specification Sheet

CY7C0837AV, CY7C0830AV
CY7C0831AV, CY7C0832AV
CY7C0832BV, CY7C0833AV
Document #: 38-06059 Rev. *S Page 21 of 28
Figure 17. Left_Port (L_Port) Write to Right_Port (R_Port) Read
[47, 48, 49]
Switching Waveforms (continued)
t
SA
t
HA
t
SW
t
HW
t
CH2
t
CL2
t
CYC2
CLK
L
R/W
L
A
n
D
n
t
CKHZ
t
HD
t
SA
A
n
t
HA
Q
n
t
DC
t
CCS
t
SD
t
CKLZ
t
CH2
t
CL2
t
CYC2
t
CD2
L_PORT
ADDRESS
L_PORT
DATA
IN
CLK
R
R/W
R
R_PORT
ADDRESS
R_PORT
DATA
OUT
Notes
47. CE
0
= OE = ADS = CNTEN = BE0 – BE1 = LOW; CE
1
= CNTRST = MRST = CNT/MSK = HIGH.
48. This timing is valid when one port is writing, and other port is reading the same location at the same time. If t
CCS
is violated, indeterminate data is Read out.
49. If t
CCS
< minimum specified value, then R_Port is Read the most recent data (written by L_Port) only (2 * t
CYC2
+ t
CD2
) after the rising edge of R_Port's clock. If t
CCS
>
minimum specified value, then R_Port is Read the most recent data (written by L_Port) (t
CYC2
+ t
CD2
) after the rising edge of R_Port's clock.
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