Synchronous Dual-Port RAM Specification Sheet

CY7C0837AV, CY7C0830AV
CY7C0831AV, CY7C0832AV
CY7C0832BV, CY7C0833AV
Document #: 38-06059 Rev. *S Page 22 of 28
Figure 18. Counter Interrupt and Retransmit
[15, 42, 50, 51, 52, 53]
Switching Waveforms (continued)
t
CH2
t
CL2
t
CYC2
CLK
3FFFD 3FFFF
INTERNAL
ADDRESS
Last_Loaded
Last_Loaded +1
t
HCM
COUNTER
3FFFE
CNTINT
t
SCINT
t
RCINT
3FFFC
CNTEN
ADS
CNT/MSK
t
SCM
Notes
50. CE
0
= OE = BE0 – BE1 = LOW; CE
1
= R/W = CNTRST = MRST = HIGH.
51. CNTINT
is always driven.
52. CNTINT
goes LOW when the unmasked portion of the address counter is incremented to the maximum value.
53. The mask register assumed to have the value of 3FFFFh.
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