Low EMI Spectrum Spread Clock Specification Sheet

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Low EMI Spectrum Spread Clock

FS781/82/84

Cypress Semiconductor Corporation • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600

Document #: 38-07029 Rev. *F Revised January 2, 2005

Features

• Spread Spectrum clock generator (SSCG) with 1×, 2×,

and 4× outputs

• 6- to 82-MHz operating frequency range

• Modulates external clocks including crystals, crystal

oscillators, or ceramic resonators

• Programmable modulation with simple R-C external

loop filter (LF)

• Center spread modulation

• 3V-5V power supply

• TTL-/CMOS-compatible outputs

• Low short-term jitter

• Low-power Dissipation

— 3.3 VDC = 37 mW – typical

— 5.0 VDC = 115 mW – typical

• Available in 8-pin SOIC and TSSOP packages

Applications

• Desktop/notebook computers

• Printers, copiers, and MFP

• Scanners and fax

• LCD displays and monitors

• CD-ROM, VCD, and DVD

• Automotive and embedded systems

• Networking, LAN/WAN

• Digital cameras and camcorders

•Modems

Benefits

• Programmable EMI reduction

• Fast time to market

• Lower cost of compliance

• No degradation in rise/fall times

• Lower component and PCB layer count

Functional Description

The Cypress FS781/82/84 are Spread Spectrum clock

generator ICs (SSCG) designed for the purpose of reducing

electromagnetic interference (EMI) found in today’s

high-speed digital systems.

The FS781/82/84 SSCG clocks use a Cypress-proprietary

technology to modulate the input clock frequency, XIN, by

modulating the frequency of the digital clock. By modulating

the reference clock the measured EMI at the fundamental and

harmonic frequencies of FSOUT is greatly reduced. This

reduction in radiated energy can significantly reduce the cost

of complying with regulatory requirements without degrading

digital waveforms.

The Cypress FS781/82/84 clocks are very simple and

versatile devices to use. By programming the two range select

lines, S0 and S1, any frequency from 6- to 82-MHz operating

range can be selected. The FS781/2/4 are designed to

operate over a very wide range of input frequencies and

provides 1×, 2×, and 4× modulated clock outputs.

The FS78x devices have a simple frequency selection table

that allows operation from 6 MHz to 82 MHz in four separate

ranges. The bandwidth of the frequency spread at FSOUT is

determined by the values of the loop filter components. The

modulation rate is determined internally by the input frequency

and the selected input frequency range.

The Bandwidth of these products can be programmed from as

little as 1.0% up to as much as 4.0% by selecting the proper

loop filter value. Refer to the Loop Filter Selection chart in

Table 2 and Table 3 for the recommended values. Due to a

wide range of application requirements, an external loop filter

(LF) is used on the FS78x products. The user can select the

exact amount of frequency modulation suitable for the appli-

cation. Using a fixed internal loop filter would severely limit

the use of a wide range of modulation bandwidths (Spread %)

to a few discrete values. Refer to FS791/2/4 products for appli-

cations requiring 80- to 140-MHz frequency range.

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Summary of content (12 pages)

PAGE 1
FS781/82/84 Low EMI Spectrum Spread Clock Features Functional Description • Spread Spectrum clock generator (SSCG) with 1×, 2×, and 4× outputs • 6- to 82-MHz operating frequency range • Modulates external clocks including crystals, crystal oscillators, or ceramic resonators • Programmable modulation with simple R-C external loop filter (LF) • Center spread modulation • 3V-5V power supply • TTL-/CMOS-compatible outputs The Cypress FS781/82/84 are Spread Spectrum clock generator ICs (SSCG) designed for th
PAGE 2
FS781/82/84 Pin Configuration Block Diagram Loop Filter 4(6) 250 K Xin Reference Divider 1(3) Phase Detector 8 pF Xin 1 8 VDD Xout 2 7 S0 S1 3 6 FSOUT 4 5 VSS LF FS78x VCO 8 Pin SOIC Package 10 pF.
PAGE 3
FS781/82/84 Table 2. FS781/82/84 Recommended Loop Filter Values C7 (pF) @ +3.3 VDC ±5% (R6 = 3.3K)[1, 2, 3, 4] Input MHz S1 6 0 S0 BW = 1.0%[3] BW = 1.5%[3] BW = 2.0%[3] BW = 2.5%[3] BW = 3.0%[3] BW = 3.5%[3] BW = 4.
PAGE 4
FS781/82/84 Table 3. FS781/82/84 Recommended Loop Filter Values C7 (pF) @ +5.0 VDC ±5% (R6 = 3.3K)[1, 2, 3, 4] Input MHz S1 S0 6 0 0 BW = 1.0%[3] BW = 1.5%[3] BW = 2.0%[3] BW = 2.5%[3] BW = 3.0%[3] BW = 3.5%[3] BW = 4.
PAGE 5
FS781/82/84 Table 4. Modulation Rate Divider Ratios S1 S0 Input Frequency Range (MHz) Modulation Divider Number 0 0 6 to 16 120 0 1 16 to 32 240 1 0 32 to 66 480 1 1 66 to 82 720 SSCG Modulation Profile The digital control inputs S0 and S1 determine the modulation frequency of FS781/2/4 products. The input frequency is divided by a fixed number, depending on the operating range that is selected. The modulation frequency of the FS78x can be determined from Table 4.
PAGE 6
FS781/82/84 50% 50% Tc = 50 ns. Figure 2. 20-MHz Unmodulated Clock From the above parameters, the output clock at FSOUT will be sweeping symmetrically around a center frequency of 20 MHz. The minimum and maximum extremes of this clock will be +200 kHz and –200 kHz. So we have a clock that is sweeping from 19.8 MHz to 20.2 MHz and back again. If we were to look at this clock on a spectrum analyzer we would see the picture in Figure 3. Keep in mind that this is a drawing of a perfect clock with no noise.
PAGE 7
FS781/82/84 Crystal is 20 MHz is 1st Order with 18 pF load capacitance. C2 1 If Crystal load capacitance is different than 18 pF, C1 and C2 must be re-calculated. For third overtone crystals, a parallel or series resonant trap is required. 20 MHz 27 pF Xin VDD 8 0.1 uF Y1 C3 2 VDD C1 Xout S0 7 FS781 (SOIC) 27 pF 3 4 Mount loop filter components as close to LF pin as possible.
PAGE 8
FS781/82/84 Absolute Maximum Ratings[6] This device contains circuitry to protect the input against damage due to high static voltages or electric fields; however, precautions should be taken to avoid application of any voltage higher than the absolute maximum rated voltages to this circuit. For proper operation, VIN and VOUT should be constrained to the range, VSS < (VIN or VOUT) < VDD. All digital inputs are tied high or low internally. Refers to electrical specifications for operating supply range.
PAGE 9
FS781/82/84 Table 7. Timing Electrical Characteristics VDD = 3.3V and 5.0V ±10%, TA = 0°C to 70°C, CL = 15 pF, XIN = 48 MHz (continued) Parameter Description Min. Typ. Max. Unit CCJ FSOUT, Cycle-to-Cycle Jitter, 48 MHz @ 3.30 VDC (Pin 6) – 320 370 ps CCJ FSOUT, Cycle-to-Cycle Jitter, 48 MHz @ 5.0 VDC (Pin 6) – 310 360 ps CCJ FSOUT, Cycle-to-Cycle Jitter, 72 MHz @ 3.30 VDC (Pin 6) – 270 325 ps CCJ FSOUT, Cycle-to-Cycle Jitter, 72 MHz @ 5.0 VDC (Pin 6) – 390 440 ps Table 8.
PAGE 10
FS781/82/84 Marking Example Cypress FS781BT Date Code, Lot # Cypress FS781BS Date Code, Lot # FS781 B S Package S = SOIC T = TSSOP Revision Cypress Device Driver Package Drawing and Dimensions 8 Lead (150 Mil) SOIC S08 8-lead (150-Mil) SOIC S8 PIN 1 ID 4 1 1. DIMENSIONS IN INCHES[MM] MIN. MAX. 2. PIN 1 ID IS OPTIONAL, ROUND ON SINGLE LEADFRAME RECTANGULAR ON MATRIX LEADFRAME 0.150[3.810] 0.157[3.987] 3. REFERENCE JEDEC MS-012 0.230[5.842] 0.244[6.197] 4. PACKAGE WEIGHT 0.07gms PART # S08.
PAGE 11
FS781/82/84 Package Drawing and Dimensions (continued) 8-Lead Thin Shrunk Small Outline Package (4.40 MM Body) Z8 PIN 1 ID 1 DIMENSIONS IN MM[INCHES] MIN. MAX. 6.25[0.246] 6.50[0.256] 4.30[0.169] 4.50[0.177] 8 0.65[0.025] BSC. 0.19[0.007] 0.30[0.012] 1.10[0.043] MAX. 0.25[0.010] BSC GAUGE PLANE 0°-8° 0.076[0.003] 0.85[0.033] 0.95[0.037] 0.05[0.002] 0.15[0.006] 2.90[0.114] 3.10[0.122] SEATING PLANE 0.50[0.020] 0.70[0.027] 0.09[[0.003] 0.20[0.
PAGE 12
FS781/82/84 Document History Page Document Title: FS781/82/84 Low EMI Spectrum Spread Clock Document Number: 38-07029 REV. ECN NO. Issue Date Orig. of Change ** 106948 06/07/01 IKA Convert from IMI to Cypress *A 111654 02/27/02 IKL Add new marking suffix for SOIC packages. Converted to FrameMaker. Description of Change *B 118355 08/30/02 RGL Swap the location of S0 and S1 in tables 2 and 3 in pages 2,3 and 4.