Independent Clock Serializer and Reclocking Deserializer Specification Sheet

ManualsBrandsCypress ManualsClockHOTLink II CYV15G0104TRB

Independent Clock HOTLink II™ Serializer and

Reclocking Deserialize

CYV15G0104TRB

Cypress Semiconductor Corporation • 3901 North First Street • San Jose, CA 95134 • 408-943-2600

Document #: 38-02100 Rev. *B Revised July 8, 2005

Features

• Second-generation HOTLink

technology

• Compliant to SMPTE 292M and SMPTE 259M video

standards

• Single channel video serializer plus single channel

video reclocking deserializer

— 195- to 1500-Mbps serial data signaling rate

— Simultaneous operation at different signaling rates

• Supports reception of either 1.485 or 1.485/1.001 Gbps

data rate with the same training clock

• Internal phase-locked loops (PLLs) with no external

PLL components

• Supports half-rate and full-rate clocking

• Selectable differential PECL-compatible serial inputs

— Internal DC-restoration

• Redundant differential PECL-compatible serial outputs

— No external bias resistors required

— Internal source termination

— Signaling-rate controlled edge-rates

• Synchronous LVTTL parallel interface

• JTAG boundary scan

• Built-In Self-Test (BIST) for at-speed link testing

• Link Quality Indicator

— Analog signal detect

— Digital signal detect

• Low-power 1.8W @ 3.3V typical

• Single 3.3V supply

• Thermally enhanced BGA

• Pb-Free package option available

•0.25µ BiCMOS technology

Functional Description

The CYV15G0104TRB Independent Clock HOTLink II™

Serializer and Reclocking Deserializer is a point-to-point or

point-to-multipoint communications building block enabling

transfer of data over a variety of high-speed serial links

including SMPTE 292M and SMPTE 259M video applications.

It supports signaling rates in the range of 195 to 1500 Mbps

per serial link. The transmit and receive channels are

independent and can operate simultaneously at different

rates. The transmit channel accepts 10-bit parallel characters

in an Input Register and converts them to serial data. The

receive channel accepts serial data and converts it to 10-bit

parallel characters and presents these characters to an Output

retransmitted through the reclocker serial outputs. Figure 1

illustrates typical connections between independent video co-

processors and corresponding CYV15G0104TRB chips.

The CYV15G0104TRB satisfies the SMPTE 259M and

SMPTE 292M compliance as per SMPTE EG34-1999 Patho-

logical Test Requirements.

As a second-generation HOTLink device, the

CYV15G0104TRB extends the HOTLink family with enhanced

levels of integration and faster data rates, while maintaining

serial-link compatibility (data and BIST) with other HOTLink

devices. The transmit (TX) channel of the CYV15G0104TRB

HOTLink II device accepts scrambled 10-bit transmission

characters. These characters are serialized and output from

dual Positive ECL (PECL) compatible differential trans-

mission-line drivers at a bit-rate of either 10- or 20-times the

input reference clock for that channel.

The receive (RX) channel of the CYV15G0104TRB HOTLink

II device accepts a serial bit-stream from one of two selectable

PECL-compatible differential line receivers, and using a

completely integrated Clock and Data Recovery PLL, recovers

the timing information necessary for data reconstruction. The

recovered bit-stream is reclocked and retransmitted through

the reclocker serial outputs. Also, the recovered serial data is

deserialized and presented to the destination host system.

The transmit and receive channels contain an independent

BIST pattern generator and checker, respectively. This BIST

hardware allows at-speed testing of the high-speed serial data

paths in each transmit and receive section, and across the

interconnecting links.

Figure 1. HOTLink II™ System Connections

Video Coprocessor

Serial

Links

Independent

CYV15G0104TRB

Independent

Device

Channel

CYV15G0104TRB

Channel

Reclocked

Output

Reclocked

Output

[+] Feedback

Summary of content (27 pages)

PAGE 1
CYV15G0104TRB Independent Clock HOTLink II™ Serializer and Reclocking Deserializer Features transfer of data over a variety of high-speed serial links including SMPTE 292M and SMPTE 259M video applications. It supports signaling rates in the range of 195 to 1500 Mbps per serial link. The transmit and receive channels are independent and can operate simultaneously at different rates. The transmit channel accepts 10-bit parallel characters in an Input Register and converts them to serial data.
PAGE 2
CYV15G0104TRB The CYV15G0104TRB is ideal for SMPTE applications where different data rates and serial interface standards are necessary for each channel. Some applications include multi- format routers, switchers, format converters, SDI monitors, cameras, and camera control units. x10 x10 Deserializer Phase Align Buffer REFCLKB± TXDB[9:0] TRGCLKA± RXDA[9:0] CYV15G0104TRB Serializer and Reclocking Deserializer Logic Block Diagram Document #: 38-02100 Rev.
PAGE 3
CYV15G0104TRB Reclocking Deserializer Path Block Diagram RESET TRST JTAG Boundary Scan Controller TRGRATEA x2 TRGCLKA TMS TCLK TDI TDO SDASEL[2..1]A[1:0] LDTDEN Clock & Data Recovery PLL INA2+ INA2– ULCA 10 10 Output Register INA1+ INA1– Shifter INSELA BIST LFSR LFIA Receive Signal Monitor 10 RXDA[9:0] BISTSTA ÷2 SPDSELA RXCLKA+ RXCLKA– RXBISTA[1:0] RXRATEA RXPLLPDA Recovered Character Clock Recovered Serial Data Reclocker Output PLL Clock Multiplier RECLKOA Register ROE[2..
PAGE 4
CYV15G0104TRB Pin Configuration (Top View)[1] A B C D E F G H J K L M N P R T U V W Y 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 NC NC NC NC VCC NC TOUT B1– GND GND TOUT B2– IN A1– ROUT A1– GND IN A2– ROUT A2– VCC VCC NC VCC NC VCC NC VCC NC VCC VCC TOUT B1+ GND NC TOUT B2+ IN A1+ ROUT A1+ GND IN A2+ ROUT A2+ VCC NC NC NC NC TDI TMS VCC VCC VCC NC NC GND DATA [6] DATA [4] DATA [2] DATA [0] GND NC SPD SELB VCC LDTD EN TRST
PAGE 5
CYV15G0104TRB Pin Configuration (Bottom View)[1] A B C D E F G H J K L M N P R T U V W Y 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 NC VCC NC VCC VCC ROUT A2– IN A2– GND ROUT A1– IN A1– TOUT B2– GND GND TOUT B1– NC VCC NC NC NC NC NC NC NC NC VCC ROUT A2+ IN A2+ GND ROUT A1+ IN A1+ TOUT B2+ NC GND TOUT B1+ VCC VCC NC VCC NC VCC TDO GND TRST LDTD EN VCC SPD SELB NC GND DATA [0] DATA [2] DATA [4] DATA [6] GND NC NC VCC VCC
PAGE 6
CYV15G0104TRB Pin Definitions CYV15G0104TRB HOTLink II Serializer and Reclocking Deserializer Name I/O Characteristics Signal Description Transmit Path Data and Status Signals TXDB[9:0] LVTTL Input, synchronous, sampled by TXCLKB↑ or REFCLKB↑[2] Transmit Data Inputs. TXDB[9:0] data inputs are captured on the rising edge of the transmit interface clock. The transmit interface clock is selected by the TXCKSELB latch via the device configuration interface.
PAGE 7
CYV15G0104TRB Pin Definitions (continued) CYV15G0104TRB HOTLink II Serializer and Reclocking Deserializer Name BISTSTA I/O Characteristics LVTTL Output, synchronous to the RXCLKA ± output Signal Description BIST Status Output. When RXBISTA[1:0] = 10, BISTSTA (along with RXDA[1:0]) displays the status of the BIST reception. See Table 6 for the BIST status reported for each combination of BISTSTA and RXDA[1:0]. When RXBISTA[1:0] ≠ 10, BISTSTA should be ignored.
PAGE 8
CYV15G0104TRB Pin Definitions (continued) CYV15G0104TRB HOTLink II Serializer and Reclocking Deserializer Name SPDSELA SPDSELB I/O Characteristics [4] 3-Level Select static control input Signal Description Serial Rate Select. The SPDSELA and SPDSELB inputs specify the operating signalingrate range of the receive and transmit PLL, respectively. LOW = 195 – 400 MBd MID = 400 – 800 MBd HIGH = 800 – 1500 MBd. INSELA LVTTL Input, asynchronous Receive Input Selector.
PAGE 9
CYV15G0104TRB Pin Definitions (continued) CYV15G0104TRB HOTLink II Serializer and Reclocking Deserializer Name I/O Characteristics Signal Description ROE2A Internal Latch[6] Reclocker Differential Serial Output Driver 2 Enable. ROE1A Internal Latch[6] Reclocker Differential Serial Output Driver 1 Enable. PABRSTB [6] Internal Latch Transmit Clock Phase Alignment Buffer Reset. Factory Test Modes SCANEN2 LVTTL input, internal pull-down Factory Test 2. SCANEN2 input is for factory testing only.
PAGE 10
CYV15G0104TRB Phase-Align Buffer Data from the Input Register is passed to the Phase-Align Buffer, when the TXDB[9:0] input register is clocked using TXCLKBA (TXCKSELB = 0) or when REFCLKB is a half-rate clock (TXCKSELB = 1 and TXRATEB = 1). When the TXDB[9:0] input register is clocked using REFCLKB± (TXCKSELA = 1) and REFCLKB± is a full-rate clock (TXRATEB = 0), the associated Phase Alignment Buffer in the transmit path is bypassed.
PAGE 11
CYV15G0104TRB INSELA input. The Serial Line Receiver inputs are differential, and can accommodate wire interconnect and filtering losses or transmission line attenuation greater than 16 dB. For normal operation, these inputs should receive a signal of at least VIDIFF > 100 mV, or 200 mV peak-to-peak differential. Each Line Receiver can be DC- or AC-coupled to +3.3V powered fiber-optic interface modules (any ECL/PECL family, not limited to 100K PECL) or AC-coupled to +5V powered optical modules.
PAGE 12
CYV15G0104TRB performed by an integrated PLL that tracks the frequency of the transitions in the incoming bit stream and aligns the phase of the internal bit-rate clock to the transitions in the selected serial data stream. Each CDR accepts a character-rate (bit-rate ÷ 10) or halfcharacter-rate (bit-rate ÷ 20) training clock from the TRGCLKA± input.
PAGE 13
CYV15G0104TRB the device configuration interface. When RXPLLPDA = 0, the receive PLL and analog circuitry of the channel is disabled. The transmit channel is controlled by the TOE1B and the TOE2B latches via the device configuration interface. The reclocker function is controlled by the ROE1A and the ROE2A latches via the device configuration interface. When a driver is disabled via the configuration interface, it is internally powered down to reduce device power.
PAGE 14
CYV15G0104TRB Table 4. Device Configuration and Control Latch Descriptions (continued) Name Signal Description RXPLLPDA Receive Channel Enable. The initialization value of the RXPLLPDA latch = 0. RXPLLPDA selects if the receive channel is enabled or powered-down. When RXPLLPDA = 0, the receive PLL and analog circuitry are powered-down. When RXPLLPDA = 1, the receive PLL and analog circuitry are enabled. RXBISTA[1:0] Receive Bist Disable / SMPTE Receive Enable.
PAGE 15
CYV15G0104TRB Table 5.
PAGE 16
CYV15G0104TRB Monitor Data Received Receive BIST Detected LOW {BISTSTA, RXDA[0], RXDA[1]} = BIST_START (101) RX PLL Out of Lock {BISTSTA, RXDA[0], RXDA[1]} = BIST_WAIT (111) Start of BIST Detected No Yes, {BISTSTA, RXDA[0], RXDA[1]} = BIST_DATA_COMPARE (000, 001) Compare Next Character Mismatch Yes Match Auto-Abort Condition {BISTSTA, RXDA[0], RXDA[1]} = BIST_DATA_COMPARE (000, 001) No End-of-BIST State End-of-BIST State Yes, {BISTSTA, RXDA[0], RXDA[1]} = BIST_LAST_BAD (100) Yes, {BISTSTA, R
PAGE 17
CYV15G0104TRB Maximum Ratings Static Discharge Voltage.......................................... > 2000 V (per MIL-STD-883, Method 3015) (Above which the useful life may be impaired. User guidelines only, not tested.) Latch-up Current..................................................... > 200 mA Storage Temperature .................................. –65°C to +150°C Power-up Requirements Ambient Temperature with Power Applied.............................................
PAGE 18
CYV15G0104TRB CYV15G0104TRB DC Electrical Characteristics (continued) Min. Max. Unit VOLC Parameter Output LOW Voltage (VCC Referenced) Description 100Ω differential load Test Conditions VCC – 1.4 VCC – 0.7 V 150Ω differential load VCC – 1.4 VCC – 0.
PAGE 19
CYV15G0104TRB CYV15G0104TRB AC Electrical Characteristics (continued) Parameter Description tTXCLKR [16, 17, 18, 19] TXCLKB Rise Time tTXCLKF [16, 17, 18, 19] Min. Max Unit 0.2 1.7 ns 1.7 TXCLKB Fall Time 0.2 tTXDS Transmit Data Set-up Time to TXCLKB↑ (TXCKSELB = 0) 2.2 ns ns tTXDH Transmit Data Hold Time from TXCLKB↑ (TXCKSELB = 0) 1.0 fTOS TXCLKOB Clock Frequency = 1x or 2x REFCLKB Frequency 19.5 150 MHz tTXCLKO TXCLKOB Period=1/fTOS 6.66 51.
PAGE 20
CYV15G0104TRB CYV15G0104TRB AC Electrical Characteristics (continued) Parameter tTRGH tTRGL tTRGD[23] tTRGR [16, 17, 18] Description Min. Max Unit TRGCLKA HIGH Time (TRGRATEA = 1)(Half Rate) 5.9 TRGCLKA HIGH Time (TRGRATEA = 0)(Full Rate) 2.9[16] ns TRGCLKA LOW Time (TRGRATEA = 1)(Half Rate) 5.9 ns TRGCLKA LOW Time (TRGRATEA = 0)(Full Rate) 2.
PAGE 21
CYV15G0104TRB PLL Characteristics Parameter Description Condition Min. Typ. Max. Unit CYV15G0104TRB Receive PLL Characteristics Over the Operating Range tRXLOCK tRXUNLOCK Receive PLL lock to input data stream (cold start) 376k UI Receive PLL lock to input data stream 376k UI 46 UI Receive PLL Unlock Rate Capacitance [16] Parameter Description Test Conditions Max. Unit CINTTL TTL Input Capacitance TA = 25°C, f0 = 1 MHz, VCC = 3.
PAGE 22
CYV15G0104TRB CYV15G0104TRB HOTLink II Transmitter Switching Waveforms (continued) Transmit Interface TXCLKOB Timing tREFCLK tREFH TXRATE = 1 REFCLKB tREFL Note 28 tTXCLKO Note 29 TXCLKOB (internal) Transmit Interface TXCLKOB Timing tREFCLK tREFH TXRATEB = 0 tREFL Note28 REFCLKB Note29 tTXCLKO TXCLKOB Switching Waveforms for the CYV15G0104TRB HOTLink II Receiver Receive Interface Read Timing RXRATEA = 0 tRXCLKP RXCLKA+ RXCLKA– tRXDV– RXDA[9:0] tRXDV+ Notes: 28.
PAGE 23
CYV15G0104TRB Switching Waveforms for the CYV15G0104TRB HOTLink II Receiver Receive Interface Read Timing RXRATEA = 1 tRXCLKP RXCLKA+ RXCLKA– tRXDV– RXDA[9:0] tRXDV+ Bus Configuration Write Timing ADDR[2:0] DATA[6:0] tWRENP WREN tDATAS tDATAH Document #: 38-02100 Rev.
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CYV15G0104TRB Table 7.
PAGE 25
CYV15G0104TRB Table 7.
PAGE 26
CYV15G0104TRB Ordering Information Speed Ordering Code Package Name Package Type Operating Range Standard CYV15G0104TRB-BGC BL256 256-Ball Thermally Enhanced Ball Grid Array Commercial Standard CYV15G0104TRB-BGXC BL256 Pb-Free 256-Ball Thermally Enhanced Ball Grid Array Commercial Package Diagram 256-Lead L2 Ball Grid Array (27 x 27 x 1.57 mm) BL256 51-85123-*E HOTLink is a registered trademark and HOTLink II is a trademark of Cypress Semiconductor.
PAGE 27
CYV15G0104TRB Document History Page Document Title: CYV15G0104TRB Independent Clock HOTLink II™ Serializer and Reclocking Deserializer Document Number: 38-02100 REV. ECN NO. ISSUE DATE ORIG. OF CHANGE ** 244348 See ECN FRE New Data Sheet *A 338721 See ECN SUA Added Pb-Free package option availability *B 384307 See ECN AGT Revised setup and hold times (tTXDH, tTREFDS, tTREFDH, tRXDv–, tRXDv+) Document #: 38-02100 Rev.