Static RAM Specification Sheet

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CY62146ESL MoBL

4-Mbit (256K x 16) Static RAM

Cypress Semiconductor Corporation • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600

Document #: 001-43142 Rev. ** Revised January 04, 2008

Features

■ Very high speed: 45 ns

■ Wide voltage range: 2.2V–3.6V

and 4.5V–5.5V

■ Ultra low standby power

❐ Typical Standby current: 1 μA

❐ Maximum Standby current: 7 μA

■ Ultra low active power

❐ Typical active current: 2 mA at f = 1 MHz

■ Easy memory expansion with CE and OE features

■ Automatic power down when deselected

■ CMOS for optimum speed and power

■ Available in Pb-free 44-pin TSOP II package

Functional Description

The CY62146ESL is a high performance CMOS static RAM

organized as 256K words by 16 bits. This device features

advanced circuit design to provide ultra low active current. This

is ideal for providing More Battery Life™ (MoBL

) in portable

applications such as cellular telephones. The device also has an

automatic power down feature that reduces power consumption

when addresses are not toggling. Placing the device into standby

mode reduces power consumption by more than 99% when

deselected (CE

HIGH). The input and output pins (IO

through

) are placed in a high impedance state when:

■ Deselected (CE HIGH)

■ Outputs are disabled (OE HIGH)

■ Both Byte High Enable and Byte Low Enable are disabled

(BHE

, BLE HIGH)

■ Write operation is active (CE LOW and WE LOW)

To write to the device, take Chip Enable (CE

) and Write Enable

(WE

) inputs LOW. If Byte Low Enable (BLE) is LOW, then data

from IO pins (IO

through IO

) is written into the location

specified on the address pins (A

through A

). If Byte High

Enable (BHE

) is LOW, then data from IO pins (IO

through IO

)

is written into the location specified on the address pins (A

through A

To read from the device, take Chip Enable (CE

) and Output

Enable (OE

) LOW while forcing the Write Enable (WE) HIGH. If

Byte Low Enable (BLE

) is LOW, then data from the memory

location specified by the address pins appears on IO

to IO

. If

Byte High Enable (BHE

) is LOW, then data from memory

appears on IO

to IO

. See the “Truth Table” on page 10 for a

complete description of read and write modes.

For best practice recommendations, refer to the Cypress

application note AN1064, SRAM System Guidelines.

Logic Block Diagram

256K x 16

RAM Array

–IO

ROW DECODER

COLUMN DECODER

SENSE AMPS

DATA IN DRIVERS

–IO

BHE

BLE

[+] Feedback [+] Feedback

Summary of content (12 pages)

PAGE 1
CY62146ESL MoBL® 4-Mbit (256K x 16) Static RAM Features ■ Very high speed: 45 ns mode reduces power consumption by more than 99% when deselected (CE HIGH). The input and output pins (IO0 through IO15) are placed in a high impedance state when: ■ Wide voltage range: 2.2V–3.6V and 4.5V–5.
PAGE 2
CY62146ESL MoBL® Pin Configuration Figure 1.
PAGE 3
CY62146ESL MoBL® Maximum Ratings Output Current into Outputs (LOW)............................. 20 mA Exceeding the maximum ratings may impair the useful life of the device. These user guidelines are not tested. Storage Temperature .................................. –65°C to +150°C Ambient Temperature with Power Applied ............................................ –55°C to +125°C Static Discharge Voltage............................................ >2001V (MIL-STD-883, Method 3015) Latch up Current.......
PAGE 4
CY62146ESL MoBL® Capacitance Tested initially and after any design or process changes that may affect these parameters. Parameter Description CIN Input Capacitance COUT Output Capacitance Test Conditions TA = 25°C, f = 1 MHz, VCC = VCC(typ) Max Unit 10 pF 10 pF TSOP II Unit 77 °C/W 13 °C/W Thermal Resistance Tested initially and after any design or process changes that may affect these parameters.
PAGE 5
CY62146ESL MoBL® Data Retention Characteristics Over the Operating Range Parameter Description VDR VCC for Data Retention ICCDR Data Retention Current tCDR [7] Chip Deselect to Data Retention Time tR [8] Operation Recovery Time Conditions Min Typ[3] Max 1.5 CE > VCC – 0.2V, VIN > VCC – 0.2V or VIN < 0.2V VCC = 1.5V Unit V 1 7 μA 0 ns tRC ns Data Retention Waveform DATA RETENTION MODE VCC VCC(min) VDR > 1.5V tCDR VCC(min) tR CE Notes 7.
PAGE 6
CY62146ESL MoBL® Switching Characteristics Over the Operating Range [9] Parameter Description 45 ns Min Max Unit Read Cycle tRC Read Cycle Time 45 tAA Address to Data Valid tOHA Data Hold from Address Change tACE CE LOW to Data Valid 45 ns tDOE OE LOW to Data Valid 22 ns 18 ns LOW-Z[10] tLZOE OE LOW to tHZOE OE HIGH to High-Z[10, 11] tLZCE CE LOW to Low-Z[10] ns 45 10 ns 5 ns 10 High-Z[10, 11] ns ns tHZCE CE HIGH to tPU CE LOW to Power Up tPD CE HIGH to Power Down
PAGE 7
CY62146ESL MoBL® Switching Waveforms Figure 2. Read Cycle No.1: Address Transition Controlled. [13, 14] tRC RC ADDRESS tAA tOHA DATA OUT PREVIOUS DATA VALID DATA VALID Figure 3. Read Cycle No. 2: OE Controlled [14, 15] ADDRESS tRC CE tPD tHZCE tACE OE tHZOE tDOE tLZOE BHE/BLE tHZBE tDBE tLZBE HIGH IMPEDANCE HIGHIMPEDANCE DATA VALID DATA OUT tLZCE tPU VCC SUPPLY CURRENT ICC 50% 50% ISB Notes 13. The device is continuously selected. OE, CE = VIL, BHE, BLE, or both = VIL. 14.
PAGE 8
CY62146ESL MoBL® Switching Waveforms (continued) Figure 4. Write Cycle No 1: WE Controlled [12, 16, 17] tWC ADDRESS tSCE CE tAW tHA tSA tPWE WE tBW BHE/BLE OE DATA IO tSD NOTE 18 tHD DATAIN tHZOE Figure 5. Write Cycle 2: CE Controlled [12, 16, 17] tWC ADDRESS tSCE CE tSA tAW tHA tPWE WE tBW BHE/BLE OE tSD DATA IO tHD DATAIN NOTE 18 tHZOE Notes 16. Data IO is high impedance if OE = VIH. 17. If CE goes HIGH simultaneously with WE = VIH, the output remains in a high impedance state. 18.
PAGE 9
CY62146ESL MoBL® Switching Waveforms (continued) Figure 6. Write Cycle 3: WE controlled, OE LOW [17] tWC ADDRESS tSCE CE tBW BHE/BLE tAW tHA tSA tPWE WE tSD DATA IO NOTE 18 tHD DATAIN tLZWE tHZWE Figure 7. Write Cycle 4: BHE/BLE Controlled, OE LOW [17] tWC ADDRESS CE tSCE tAW tHA tBW BHE/BLE tSA tPWE WE tHZWE DATA IO NOTE 18 tSD tHD DATAIN tLZWE Document #: 001-43142 Rev.
PAGE 10
CY62146ESL MoBL® Truth Table CE WE OE BHE BLE H X X X X High-Z Inputs/Outputs Deselect/Power down Mode Standby (ISB) Power L X X H H High-Z Output Disabled Active (ICC) L H L L L Data Out (IO0–IO15) Read Active (ICC) L H L H L Data Out (IO0–IO7); IO8–IO15 in High-Z Read Active (ICC) L H L L H Data Out (IO8–IO15); IO0–IO7 in High-Z Read Active (ICC) L H H L L High-Z Output Disabled Active (ICC) L H H H L High-Z Output Disabled Active (ICC) L H
PAGE 11
CY62146ESL MoBL® Package Diagrams Figure 8. 44-Pin TSOP II, 51-85087 51-85087-*A Document #: 001-43142 Rev.
PAGE 12
CY62146ESL MoBL® Document History Page Document Title: CY62146ESL MoBL® 4-Mbit (256K x 16) Static RAM Document Number: 001-43142 REV. ECN NO. Issue Date ** 1875228 See ECN Orig. of Change Description of Change VKN/AESA New Data Sheet © Cypress Semiconductor Corporation, 2008. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product.