Static RAM Specification Sheet

CY62146ESL MoBL
®
Document #: 001-43142 Rev. ** Page 8 of 12
Figure 4. Write Cycle No 1: WE
Controlled
[12, 16, 17]
Figure 5. Write Cycle 2: CE Controlled
[12, 16, 17]
Switching Waveforms (continued)
t
HD
t
SD
t
PWE
t
SA
t
HA
t
AW
t
WC
t
HZOE
DATA
IN
NOTE 18
t
BW
t
SCE
DATA IO
ADDRESS
CE
WE
OE
BHE/BLE
t
HD
t
SD
t
PWE
t
HA
t
AW
t
SCE
t
WC
t
HZOE
DATA
IN
t
BW
t
SA
CE
ADDRESS
WE
DATA IO
OE
BHE/BLE
NOTE 18
Notes
16. Data IO is high impedance if OE
= V
IH
.
17. If CE
goes HIGH simultaneously with WE = V
IH
, the output remains in a high impedance state.
18. During this period, the IOs are in output state. Do not apply input signals.
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