Flow-Through SRAM Specification Sheet

ManualsBrandsCypress ManualsComputer HardwareNoBL CY7C1357C

9-Mbit (256K x 36/512K x 18)

Flow-Through SRAM with NoBL™ Architecture

CY7C1355C

CY7C1357C

Cypress Semiconductor Corporation • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600

Document #: 38-05539 Rev. *E Revised September 14, 2006

Features

• No Bus Latency™ (NoBL™) architecture eliminates

dead cycles between write and read cycles

• Can support up to 133-MHz bus operations with zero

wait states

— Data is transferred on every clock

• Pin compatible and functionally equivalent to ZBT™

devices

• Internally self-timed output buffer control to eliminate

the need to use OE

• Registered inputs for flow-through operation

• Byte Write capability

• 3.3V/2.5V I/O power supply (V

DDQ

)

• Fast clock-to-output times

— 6.5 ns (for 133-MHz device)

• Clock Enable (CEN

) pin to enable clock and suspend

operation

• Synchronous self-timed writes

• Asynchronous Output Enable

• Available in JEDEC-standard and lead-free 100-Pin

TQFP, lead-free and non lead-free 119-Ball BGA

package and 165-Ball FBGA package

• Three chip enables for simple depth expansion.

• Automatic Power-down feature available using ZZ

mode or CE deselect

• IEEE 1149.1 JTAG-Compatible Boundary Scan

• Burst Capability—linear or interleaved burst order

• Low standby power

Functional Description

[1]

The CY7C1355C/CY7C1357C is a 3.3V, 256K x 36/512K x 18

Synchronous Flow-through Burst SRAM designed specifically

to support unlimited true back-to-back Read/Write operations

without the insertion of wait states. The

CY7C1355C/CY7C1357C is equipped with the advanced No

Bus Latency (NoBL) logic required to enable consecutive

Read/Write operations with data being transferred on every

clock cycle. This feature dramatically improves the throughput

of data through the SRAM, especially in systems that require

frequent Write-Read transitions.

All synchronous inputs pass through input registers controlled

by the rising edge of the clock. The clock input is qualified by

the Clock Enable (CEN

) signal, which when deasserted

suspends operation and extends the previous clock cycle.

Maximum access delay from the clock rise is 6.5 ns (133-MHz

device).

Write operations are controlled by the two or four Byte Write

Select (BW

) and a Write Enable (WE) input. All writes are

conducted with on-chip synchronous self-timed write circuitry.

Three synchronous Chip Enables (CE

, CE

) and an

asynchronous Output Enable (OE

) provide for easy bank

selection and output tri-state control. In order to avoid bus

contention, the output drivers are synchronously tri-stated

during the data portion of a write sequence.

Selection Guide

133 MHz 100 MHz Unit

Maximum Access Time 6.5 7.5 ns

Maximum Operating Current 250 180 mA

Maximum CMOS Standby Current 40 40 mA

Note:

1. For best-practices recommendations, please refer to the Cypress application note System Design Guidelines on www.cypress.com.

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Summary of content (28 pages)

PAGE 1
CY7C1355C CY7C1357C 9-Mbit (256K x 36/512K x 18) Flow-Through SRAM with NoBL™ Architecture Functional Description[1] Features • No Bus Latency™ (NoBL™) architecture eliminates dead cycles between write and read cycles • Can support up to 133-MHz bus operations with zero wait states — Data is transferred on every clock • Pin compatible and functionally equivalent to ZBT™ devices • Internally self-timed output buffer control to eliminate the need to use OE • Registered inputs for flow-through operation • By
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CY7C1355C CY7C1357C 1 Logic Block Diagram – CY7C1355C (256K x 36) ADDRESS REGISTER A0, A1, A A1 D1 A0 D0 MODE CLK CEN C CE ADV/LD C BURST LOGIC Q1 A1' A0' Q0 WRITE ADDRESS REGISTER ADV/LD BWA WRITE DRIVERS WRITE REGISTRY AND DATA COHERENCY CONTROL LOGIC BWB BWC MEMORY ARRAY S E N S E A M P S BWD WE D A T A S T E E R I N G O U T P U T B U F F E R S DQs DQPA DQPB DQPC DQPD E INPUT E REGISTER OE CE1 CE2 CE3 READ LOGIC SLEEP CONTROL ZZ 2 Logic Block Diagram – CY7C1357C (512K x 18) ADDR
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CY7C1355C CY7C1357C Pin Configurations Document #: 38-05539 Rev.
PAGE 4
CY7C1355C CY7C1357C Pin Configurations (continued) Document #: 38-05539 Rev.
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CY7C1355C CY7C1357C Pin Configurations (continued) 119-Ball BGA Pinout (3 Chip Enables with JTAG) CY7C1355C (256K x 36) 1 A VDDQ 2 A 3 A 4 NC/18M 5 A 6 A 7 VDDQ B C NC/576M NC/1G CE2 A A A ADV/LD VDD A A CE3 A NC NC D E DQC DQC DQPC DQC VSS VSS NC VSS VSS DQPB DQB DQB DQB F VDDQ DQC VSS VSS DQB VDDQ G H J K DQC DQC VDDQ DQD DQC DQC VDD DQD BWC VSS NC VSS BWB VSS NC VSS DQB DQB VDD DQA DQB DQB VDDQ DQA L DQD DQD DQA VDDQ DQD BWA VSS DQA M BWD VSS DQA VDDQ N
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CY7C1355C CY7C1357C Pin Configurations (continued) 165-Ball FBGA Pinout (3 Chip enable with JTAG) CY7C1355C (256K x 36) 2 3 4 5 6 7 8 9 10 11 A B C D E F G H J K L M N P NC/576M 1 A CE1 BWC BWB CE3 CEN ADV/LD A A NC NC/1G A CE2 BWD BWA CLK WE OE NC/18M A NC DQPC DQC NC DQC VDDQ VSS VDD VSS VSS VSS VSS VSS VSS VSS VDD VDDQ VDDQ VDDQ NC DQB DQPB DQB DQC DQC VDDQ VDD VSS VSS VSS VDD VDDQ DQB DQB DQC DQC NC DQD DQC VDDQ VDD VSS VSS VSS VDD DQB
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CY7C1355C CY7C1357C Pin Definitions Name I/O Description A0, A1, A InputSynchronous Address Inputs used to select one of the address locations. Sampled at the rising edge of the CLK. A[1:0] are fed to the two-bit burst counter. BWA, BWB BWC, BWD InputSynchronous Byte Write Inputs, active LOW. Qualified with WE to conduct Writes to the SRAM. Sampled on the rising edge of CLK. WE InputSynchronous Write Enable Input, active LOW. Sampled on the rising edge of CLK if CEN is active LOW.
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CY7C1355C CY7C1357C Pin Definitions (continued) Name TMS I/O Description JTAG serial input Serial data-In to the JTAG circuit. Sampled on the rising edge of TCK. If the JTAG feature Synchronous is not being utilized, this pin can be disconnected or connected to VDD. This pin is not available on TQFP packages. TCK JTAG Clock Clock input to the JTAG circuitry. If the JTAG feature is not being utilized, this pin must be connected to VSS. This pin is not available on TQFP packages. NC – No Connects.
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CY7C1355C CY7C1357C Interleaved Burst Address Table (MODE = Floating or VDD) precaution, DQs and DQPX are automatically tri-stated during the data portion of a write cycle, regardless of the state of OE. Burst Write Accesses The CY7C1355C/CY7C1357C has an on-chip burst counter that allows the user the ability to supply a single address and conduct up to four Write operations without reasserting the address inputs.
PAGE 10
CY7C1355C CY7C1357C Truth Table[2, 3, 4, 5, 6, 7, 8] Operation Address Used CE1 CE2 CE3 ZZ ADV/LD WE BWX OE CEN CLK DQ NOP/WRITE ABORT (Begin Burst) None L H L L L L H X L L->H Tri-State WRITE ABORT (Continue Burst) Next X X X L H X H X L L->H Tri-State Current X X X L X X X X H L->H – None X X X H X X X X X X Tri-State IGNORE CLOCK EDGE (Stall) SLEEP MODE Partial Truth Table for Read/Write[2, 3, 9] Function (CY7C1355C) WE H BWA X BWB X BWC X BWD X
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CY7C1355C CY7C1357C IEEE 1149.1 Serial Boundary Scan (JTAG) Test MODE SELECT (TMS) The CY7C1355C/CY7C1357C incorporates a serial boundary scan test access port (TAP) in the BGA package only. The TQFP package does not offer this functionality. This part operates in accordance with IEEE Standard 1149.1-1900, but doesn’t have the set of functions required for full 1149.1 compliance.
PAGE 12
CY7C1355C CY7C1357C Diagram. Upon power-up, the instruction register is loaded with the IDCODE instruction. It is also loaded with the IDCODE instruction if the controller is placed in a reset state as described in the previous section. When the TAP controller is in the Capture-IR state, the two least significant bits are loaded with a binary “01” pattern to allow for fault isolation of the board-level serial test data path.
PAGE 13
CY7C1355C CY7C1357C TAP Timing 1 2 Test Clock (TCK) 3 t TH t TMSS t TMSH t TDIS t TDIH t TL 4 5 6 t CYC Test Mode Select (TMS) Test Data-In (TDI) t TDOV t TDOX Test Data-Out (TDO) DON’T CARE UNDEFINED TAP AC Switching Characteristics Over the Operating Range[10, 11] Parameter Description Min. Max.
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CY7C1355C CY7C1357C 3.3V TAP AC Test Conditions 2.5V TAP AC Test Conditions Input pulse levels ................................................ VSS to 3.3V Input pulse levels................................................. VSS to 2.5V Input rise and fall times ................................................... 1 ns Input rise and fall time .....................................................1 ns Input timing reference levels ...........................................1.
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CY7C1355C CY7C1357C Scan Register Sizes Register Name Instruction Bit Size (x36) Bit Size (x18) 3 3 Bypass 1 1 ID 32 32 Boundary Scan Order (119-ball BGA package) 69 69 Boundary Scan Order (165-ball FBGA package) 69 69 Identification Codes Instruction Code Description EXTEST 000 Captures I/O ring contents. Places the boundary scan register between TDI and TDO. Forces all SRAM outputs to High-Z state. This instruction is not 1149.1 compliant.
PAGE 16
CY7C1355C CY7C1357C 119-ball BGA Boundary Scan Order CY7C1355C (256K x 36) CY7C1357C (512K x 18) Bit# ball ID Signal Name Bit# ball ID Signal Name Bit# ball Id Signal Name Bit# ball Id Signal Name 1 K4 CLK 37 R6 A 1 K4 CLK 37 R6 A 2 H4 WE 38 T5 A 2 H4 WE 38 T5 A 3 M4 CEN 39 T3 A 3 M4 CEN 39 T3 A 4 F4 OE 40 R2 A 4 F4 OE 40 R2 A 5 B4 ADV/LD 41 R3 MODE 5 B4 ADV/LD 41 R3 MODE 6 G4 A 42 P2 DQPD 6 G4 A 42 Internal Internal 7 C3
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CY7C1355C CY7C1357C 165-ball FBGA Boundary Scan Order CY7C1355C (256K x 36) CY7C1357C (512K x 18) Bit# ball ID Signal Name Bit# ball ID Signal Name Bit# ball ID Signal Name Bit# ball ID Signal Name 1 B6 CLK 37 R4 A 1 B6 CLK 37 R4 A 2 B7 WE 38 P4 A 2 B7 WE 38 P4 A 3 A7 CEN 39 R3 A 3 A7 CEN 39 R3 A 4 B8 OE 40 P3 A 4 B8 OE 40 P3 A 5 A8 ADV/LD 41 R1 MODE 5 A8 ADV/LD 41 R1 MODE 6 A9 A 42 N1 DQPD 6 A9 A 42 Internal Internal 7 B
PAGE 18
CY7C1355C CY7C1357C Maximum Ratings DC Input Voltage ................................... –0.5V to VDD + 0.5V (Above which the useful life may be impaired. For user guidelines, not tested.) Storage Temperature ................................. –65°C to +150°C Ambient Temperature with Power Applied............................................. –55°C to +125°C Current into Outputs (LOW)......................................... 20 mA Static Discharge Voltage...........................................
PAGE 19
CY7C1355C CY7C1357C Capacitance[15] Parameter Description CIN Input Capacitance CCLK Clock Input Capacitance CI/O Input/Output Capacitance Test Conditions 100 TQFP Max. 119 BGA Max. 165 FBGA Max. TA = 25°C, f = 1 MHz, VDD = 3.3V. VDDQ = 2.5V 5 5 5 pF 5 5 5 pF 5 7 7 pF 100 TQFP Package 119 BGA Package 165 FBGA Package Unit 29.41 34.1 16.8 °C/W 6.31 14.0 3.
PAGE 20
CY7C1355C CY7C1357C Switching Characteristics Over the Operating Range [16, 17] –133 Parameter tPOWER Description Min. [18] VDD(Typical) to the First Access –100 Max. Min. Max. Unit 1 1 ms Clock tCYC Clock Cycle Time 7.5 10 ns tCH Clock HIGH 3.0 4.0 ns tCL Clock LOW 3.0 4.0 ns Output Times tCDV Data Output Valid after CLK Rise tDOH Data Output Hold after CLK Rise [19, 20, 21] 6.5 2.0 7.5 2.0 ns tCLZ Clock to Low-Z tCHZ Clock to High-Z[19, 20, 21] 3.5 3.
PAGE 21
CY7C1355C CY7C1357C Switching Waveforms Read/Write Waveforms[22, 23, 24] 1 2 3 tCYC 4 5 6 7 8 9 A5 A6 A7 10 CLK tCENS tCENH tCES tCEH tCH tCL CEN CE ADV/LD WE BWX A1 ADDRESS tAS A2 A4 A3 tCDV tAH tDOH tCLZ DQ D(A1) tDS D(A2) Q(A3) D(A2+1) tOEV Q(A4+1) Q(A4) tOELZ WRITE D(A1) WRITE D(A2) D(A5) Q(A6) D(A7) WRITE D(A7) DESELECT tOEHZ tDH OE COMMAND tCHZ BURST WRITE D(A2+1) READ Q(A3) READ Q(A4) DON’T CARE BURST READ Q(A4+1) tDOH WRITE D(A5) READ Q(A6) U
PAGE 22
CY7C1355C CY7C1357C Switching Waveforms (continued) NOP, STALL and DESELECT Cycles[22, 23, 25] 1 2 3 tCYC 4 5 6 7 8 9 A5 A6 A7 10 CLK tCENS tCENH tCH tCL CEN tCES tCEH CE ADV/LD WE BWX A1 ADDRESS tAS A2 A4 A3 tCDV tAH tDOH tCLZ DQ D(A1) tDS D(A2) Q(A3) D(A2+1) tOEV Q(A4+1) Q(A4) tOELZ WRITE D(A1) WRITE D(A2) D(A5) Q(A6) D(A7) WRITE D(A7) DESELECT tOEHZ tDH OE COMMAND tCHZ BURST WRITE D(A2+1) READ Q(A3) READ Q(A4) DON’T CARE BURST READ Q(A4+1) tDOH WRITE
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CY7C1355C CY7C1357C Switching Waveforms (continued) ZZ Mode Timing[26, 27] CLK t ZZ ZZ I t ZZREC t ZZI SUPPLY I DDZZ t RZZI ALL INPUTS (except ZZ) Outputs (Q) DESELECT or READ Only High-Z DON’T CARE Notes: 26. Device must be deselected when entering ZZ mode. See truth table for all possible signal conditions to deselect the device. 27. DQs are in high-Z when exiting ZZ sleep mode. Document #: 38-05539 Rev.
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CY7C1355C CY7C1357C Ordering Information Not all of the speed, package and temperature ranges are available. Please contact your local sales representative or visit www.cypress.com for actual products offered. Speed (MHz) 133 Ordering Code CY7C1355C-133AXC Package Diagram Part and Package Type 51-85050 100-Pin Thin Quad Flat Pack (14 x 20 x 1.4 mm) Lead-Free Operating Range Commercial CY7C1357C-133AXC CY7C1355C-133BGC 51-85115 119-ball Ball Grid Array (14 x 22 x 2.
PAGE 25
CY7C1355C CY7C1357C Package Diagrams 100-Pin Thin Plastic Quad Flatpack (14 x 20 x 1.4 mm) (51-85050) 16.00±0.20 1.40±0.05 14.00±0.10 81 100 80 1 20.00±0.10 22.00±0.20 0.30±0.08 0.65 TYP. 30 12°±1° (8X) SEE DETAIL A 51 31 50 0.20 MAX. R 0.08 MIN. 0.20 MAX. 0.10 1.60 MAX. 0° MIN. SEATING PLANE STAND-OFF 0.05 MIN. 0.15 MAX. 0.25 NOTE: 1. JEDEC STD REF MS-026 GAUGE PLANE 0°-7° R 0.08 MIN. 0.20 MAX. 2.
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CY7C1355C CY7C1357C Package Diagrams (continued) 119-Ball BGA (14 x 22 x 2.4 mm) (51-85115) Ø0.05 M C Ø0.25 M C A B A1 CORNER Ø0.75±0.15(119X) Ø1.00(3X) REF. 1 2 3 4 5 6 7 7 6 5 4 3 2 1 A A B B C D 1.27 C D E E F F H 19.50 J K L 20.32 G H 22.00±0.20 G J K L M 10.16 M N P N P R R T T U U 1.27 0.70 REF. A 3.81 7.62 30° TYP. 14.00±0.20 0.15(4X) 0.15 C 2.40 MAX. B 0.90±0.05 0.25 C 12.00 51-85115-*B C Document #: 38-05539 Rev. *E 0.60±0.10 0.
PAGE 27
CY7C1355C CY7C1357C Package Diagrams (continued) 165 FBGA 13 x 15 x 1.40 MM BB165D/BW165D 165-Ball FBGA (13 x 15 x 1.4 mm) (51-85180) BOTTOM VIEW PIN 1 CORNER BOTTOM VIEW TOP VIEW PIN 1 CORNER TOP VIEW Ø0.05 M C Ø0.25 MØ0.05 CAB MC PIN 1 CORNER Ø0.25 M C A B Ø0.50 -0.06 (165X) PIN 1 CORNER 1 2 +0.14 4 2 5 3 6 4 7 5 8 6 9 7 10 11 8 9 11 10 11 10 9 11 8 10 7 9 6 8 5 7 Ø0.50 -0.06 (165X) 4 6 1 3 +0.14 2 5 4 3 2 1A B A C B C B D C D C E D F 1.
PAGE 28
CY7C1355C CY7C1357C Document History Page Document Title: CY7C1355C/CY7C1357C 9-Mbit (256K x 36/512K x 18) Flow-Through SRAM with NoBL™ Architecture Document Number: 38-05539 REV. ECN NO. Issue Date Orig.