Flow-Through SRAM Specification Sheet

ManualsBrandsCypress ManualsComputer HardwareNoBL CY7C1371D

18-Mbit (512K x 36/1M x 18)

Flow-Through SRAM with NoBL™ Architecture

CY7C1371D

CY7C1373D

Cypress Semiconductor Corporation • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600

Document #: 38-05556 Rev. *F Revised July 09, 2007

Features

• No Bus Latency™ (NoBL™) architecture eliminates dead

cycles between write and read cycles

• Supports up to 133-MHz bus operations with zero wait

states

— Data is transferred on every clock

• Pin-compatible and functionally equivalent to ZBT™

devices

• Internally self-timed output buffer control to eliminate the

need to use OE

• Registered inputs for flow through operation

• Byte Write capability

• 3.3V/2.5V IO power supply (V

DDQ

)

• Fast clock-to-output times

— 6.5 ns (for 133-MHz device)

• Clock Enable (CEN

) pin to enable clock and suspend

operation

• Synchronous self-timed writes

• Asynchronous Output Enable

• Available in JEDEC-standard Pb-free 100-pin TQFP,

Pb-free and non-Pb-free 119-Ball BGA and 165-Ball FBGA

package.

• Three chip enables for simple depth expansion

• Automatic Power down feature available using ZZ mode or

CE deselect

• IEEE 1149.1 JTAG-Compatible Boundary Scan

• Burst Capability — linear or interleaved burst order

• Low standby power

Functional Description

[1]

The CY7C1371D/CY7C1373D is a 3.3V, 512K x 36/1M x 18

Synchronous flow through Burst SRAM designed specifically

to support unlimited true back-to-back Read/Write operations

with no wait state insertion. The CY7C1371D/CY7C1373D is

equipped with the advanced No Bus Latency (NoBL) logic

required to enable consecutive Read/Write operations with

data being transferred on every clock cycle. This feature

dramatically improves the throughput of data through the

SRAM, especially in systems that require frequent Write-Read

transitions.

All synchronous inputs pass through input registers controlled

by the rising edge of the clock. The clock input is qualified by

the Clock Enable (CEN

) signal, which when deasserted

suspends operation and extends the previous clock cycle.

Maximum access delay from the clock rise is 6.5 ns (133-MHz

device).

Write operations are controlled by the two or four Byte Write

Select (BW

) and a Write Enable (WE) input. All writes are

conducted with on-chip synchronous self-timed write circuitry.

Three synchronous Chip Enables (CE

, CE

) and an

asynchronous Output Enable (OE

) provide for easy bank

selection and output tri-state control. To avoid bus contention,

the output drivers are synchronously tri-stated during the data

portion of a write sequence.

Selection Guide

133 MHz 100 MHz Unit

Maximum Access Time 6.5 8.5 ns

Maximum Operating Current 210 175 mA

Maximum CMOS Standby Current 70 70 mA

Note:

1. For best-practices recommendations, please refer to the Cypress application note System Design Guidelines on www.cypress.com.

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Summary of content (29 pages)

PAGE 1
CY7C1371D CY7C1373D 18-Mbit (512K x 36/1M x 18) Flow-Through SRAM with NoBL™ Architecture Functional Description[1] Features • No Bus Latency™ (NoBL™) architecture eliminates dead cycles between write and read cycles • Supports up to 133-MHz bus operations with zero wait states — Data is transferred on every clock • Pin-compatible and functionally equivalent to ZBT™ devices • Internally self-timed output buffer control to eliminate the need to use OE • Registered inputs for flow through operation • Byte W
PAGE 2
CY7C1371D CY7C1373D Logic Block Diagram – CY7C1371D (512K x 36) ADDRESS REGISTER A0, A1, A A1 D1 A0 D0 MODE CLK CEN C CE ADV/LD C BURST LOGIC Q1 A1' A0' Q0 WRITE ADDRESS REGISTER ADV/LD BW A WRITE DRIVERS WRITE REGISTRY AND DATA COHERENCY CONTROL LOGIC BW B BW C MEMORY ARRAY S E N S E A M P S BW D WE INPUT REGISTER OE CE1 CE2 CE3 D A T A S T E E R I N G O U T P U T B U F F E R S DQs DQP A DQP B DQP C DQP D E E READ LOGIC SLEEP CONTROL ZZ Logic Block Diagram – CY7C1373D (1M x 18) A
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CY7C1371D CY7C1373D Pin Configurations A 42 43 44 45 46 47 48 49 50 NC/36M A A A A A A A 41 NC/72M 40 37 A0 VSS 36 A1 VDD 35 A 39 34 A NC/144M 33 A 38 32 NC/288M 31 Document #: 38-05556 Rev.
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CY7C1371D CY7C1373D Pin Configurations (continued) A 42 43 44 45 46 47 48 49 50 NC/36M A A A A A A A 41 NC/72M 40 37 A0 VSS 36 A1 VDD 35 A 39 34 A NC/144M 33 A 38 32 NC/288M 31 Document #: 38-05556 Rev.
PAGE 5
CY7C1371D CY7C1373D Pin Configurations (continued) 119-Ball BGA Pinout CY7C1371D (512K x 36) A 1 VDDQ 2 A 3 A 4 A 5 A 6 A 7 VDDQ B C NC/576M NC/1G CE2 A A A ADV/LD VDD A A CE3 A NC NC D E DQC DQC DQPC DQC VSS VSS NC CE1 VSS VSS DQPB DQB DQB DQB F VDDQ DQC VSS VSS DQB VDDQ G H J K DQC DQC VDDQ DQD DQC DQC VDD DQD BWC VSS NC VSS BWB VSS NC VSS DQB DQB VDD DQA DQB DQB VDDQ DQA BWA VSS DQA DQA DQA VDDQ VSS DQA DQA L DQD DQD M VDDQ DQD BWD VSS N DQD DQD VS
PAGE 6
CY7C1371D CY7C1373D Pin Configurations (continued) 165-Ball FBGA Pinout CY7C1371D (512K x 36) 2 3 4 5 6 7 8 9 10 11 A B C D E F G H J K L M N P NC/576M 1 A CE1 BWC BWB CE3 CEN ADV/LD A A NC NC/1G A CE2 BWD BWA CLK WE OE A A NC DQPC DQC NC DQC VDDQ VSS VDD VSS VSS VSS VSS VSS VSS VSS VDD VDDQ VDDQ NC DQB DQPB DQB R MODE VDDQ DQC DQC VDDQ VDD VSS VSS VSS VDD VDDQ DQB DQB DQC DQC VDDQ VDD VSS VSS VSS VDD VDDQ DQB DQB DQC NC DQD DQC NC DQ
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CY7C1371D CY7C1373D Pin Definitions Name IO Description A0, A1, A InputAddress Inputs used to select one of the address locations. Sampled at the rising edge of the Synchronous CLK. A[1:0] are fed to the two-bit burst counter. BWA, BWB BWC, BWD InputByte Write Inputs, Active LOW. Qualified with WE to conduct writes to the SRAM. Sampled on Synchronous the rising edge of CLK. WE InputWrite Enable Input, Active LOW. Sampled on the rising edge of CLK if CEN is active LOW.
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CY7C1371D CY7C1373D Pin Definitions (continued) Name IO Description TDO JTAG serial Serial data-out to the JTAG circuit. Delivers data on the negative edge of TCK. If the JTAG feature is not being used, this pin must be left unconnected. This pin is not available on TQFP output Synchronous packages. TDI JTAG serial Serial data-In to the JTAG circuit. Sampled on the rising edge of TCK. If the JTAG feature is not being used, this pin can be left floating or connected to VDD through a pull up resistor.
PAGE 9
CY7C1371D CY7C1373D details) inputs is latched into the device and the write is complete. Additional accesses (Read/Write/Deselect) can be initiated on this cycle. The data written during the Write operation is controlled by BWX signals. The CY7C1371D/CY7C1373D provides byte write capability that is described in the truth table. Asserting the Write Enable input (WE) with the selected Byte Write Select input selectively writes to only the desired bytes.
PAGE 10
CY7C1371D CY7C1373D Truth Table[2, 3, 4, 5, 6, 7, 8] Operation Address Used CE1 CE2 CE3 ZZ ADV/LD Deselect Cycle None H X X L L X X X L L->H Tri-State Deselect Cycle None X X H L L X X X L L->H Tri-State Deselect Cycle None X L X L L X X X L L->H Tri-State Continue Deselect Cycle None X X X L H X X X L L->H Tri-State Read Cycle (Begin Burst) External L H L L L H X L L L->H Data Out (Q) Next X X X L H X X L L L->H Data Out (Q) NO
PAGE 11
CY7C1371D CY7C1373D IEEE 1149.1 Serial Boundary Scan (JTAG) Test Data-In (TDI) The CY7C1371D/CY7C1373D incorporates a serial boundary scan test access port (TAP).This part is fully compliant with 1149.1. The TAP operates using JEDEC-standard 3.3V or 2.5V IO logic levels. The CY7C1371D/CY7C1373D contains a TAP controller, instruction register, boundary scan register, bypass register, and ID register.
PAGE 12
CY7C1371D CY7C1373D instruction if the controller is placed in a reset state as described in the previous section. access between the TDI and TDO in the shift-DR controller state. When the TAP controller is in the Capture-IR state, the two least significant bits are loaded with a binary “01” pattern to allow for fault isolation of the board level serial test data path. IDCODE Bypass Register To save time when serially shifting data through registers, it is sometimes advantageous to skip certain chips.
PAGE 13
CY7C1371D CY7C1373D This bit can be set by entering the SAMPLE/PRELOAD or EXTEST command, and then shifting the desired bit into that cell, during the “Shift-DR” state. During “Update-DR,” the value loaded into that shift-register cell latches into the preload register. When the EXTEST instruction is entered, this bit directly controls the output Q-bus pins.
PAGE 14
CY7C1371D CY7C1373D TAP AC Switching Characteristics Over the Operating Range[10, 11] Parameter Description Min Max Unit 20 MHz Clock tTCYC TCK Clock Cycle Time tTF TCK Clock Frequency tTH TCK Clock HIGH time 20 ns tTL TCK Clock LOW time 20 ns 50 ns Output Times tTDOV TCK Clock LOW to TDO Valid tTDOX TCK Clock LOW to TDO Invalid 0 ns tTMSS TMS Setup to TCK Clock Rise 5 ns tTDIS TDI Setup to TCK Clock Rise 5 ns tCS Capture Setup to TCK Rise 5 ns tTMSH TMS Hold after T
PAGE 15
CY7C1371D CY7C1373D 3.3V TAP AC Test Conditions 2.5V TAP AC Test Conditions Input pulse levels ............................................... .VSS to 3.3V Input pulse level................................................... VSS to 2.5V Input rise and fall times ................................................... 1 ns Input rise and fall time .....................................................1 ns Input timing reference levels ...........................................1.
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CY7C1371D CY7C1373D Identification Register Definitions CY7C1371D (512K X 36) CY7C1373D (1M X 18) 000 000 Device Depth (28:24) 01011 01011 Device Width (23:18) 001001 001001 Defines memory type and architecture Cypress Device ID (17:12) 100101 010101 Defines width and density 00000110100 00000110100 1 1 Instruction Field Revision Number (31:29) Cypress JEDEC ID Code (11:1) ID Register Presence Indicator (0) Description Describes the version number Reserved for internal use Allows uniq
PAGE 17
CY7C1371D CY7C1373D 119-Ball BGA Boundary Scan Order [13, 14] Bit # Ball ID Bit # Ball ID Bit # Ball ID Bit # Ball ID 1 H4 23 F6 45 G4 67 L1 2 T4 24 E7 46 A4 68 M2 3 T5 25 D7 47 G3 69 N1 4 T6 26 H7 48 C3 70 P1 5 R5 27 G6 49 B2 71 K1 6 L5 28 E6 50 B3 72 L2 7 R6 29 D6 51 A3 73 N2 8 U6 30 C7 52 C2 74 P2 9 R7 31 B7 53 A2 75 R3 10 T7 32 C6 54 B1 76 T1 11 P6 33 A6 55 C1 77 R1 12 N7 34 C5 56 D2 78 T2 13 M6 35
PAGE 18
CY7C1371D CY7C1373D 165-Ball BGA Boundary Scan Order [13, 15] Bit # Ball ID Bit # Ball ID Bit # Ball ID 1 N6 31 D10 61 G1 2 N7 32 C11 62 D2 3 N10 33 A11 63 E2 4 P11 34 B11 64 F2 5 P8 35 A10 65 G2 6 R8 36 B10 66 H1 7 R9 37 A9 67 H3 8 P9 38 B9 68 J1 9 P10 39 C10 69 K1 10 R10 40 A8 70 L1 11 R11 41 B8 71 M1 12 H11 42 A7 72 J2 13 N11 43 B7 73 K2 14 M11 44 B6 74 L2 15 L11 45 A6 75 M2 16 K11 46 B5 76 N1 17 J11
PAGE 19
CY7C1371D CY7C1373D Maximum Ratings DC Input Voltage ................................... –0.5V to VDD + 0.5V Exceeding maximum ratings may impair the useful life of the device. These user guidelines are not tested. Storage Temperature ................................. –65°C to +150°C Ambient Temperature with Power Applied............................................. –55°C to +125°C Supply Voltage on VDD Relative to GND........ –0.5V to +4.6V Supply Voltage on VDDQ Relative to GND ...... –0.
PAGE 20
CY7C1371D CY7C1373D Capacitance[18] Parameter Description CIN Input Capacitance CCLK Clock Input Capacitance CIO Input/Output Capacitance Test Conditions 100 TQFP Package 119 BGA Package 165 FBGA Package Unit 5 8 9 pF 5 8 9 pF 5 8 9 pF 100 TQFP Package 119 BGA Package 165 FBGA Package Unit 28.66 23.8 20.7 °C/W 4.08 6.2 4.0 °C/W TA = 25°C, f = 1 MHz, VDD = 3.3V VDDQ = 2.
PAGE 21
CY7C1371D CY7C1373D Switching Characteristics Over the Operating Range[23, 24] 133 MHz Parameter tPOWER Description [19] Min Max 100 MHz Min Max Unit 1 1 ms Clock tCYC Clock Cycle Time 7.5 10 ns tCH Clock HIGH 2.1 2.5 ns tCL Clock LOW 2.1 2.5 ns Output Times tCDV Data Output Valid After CLK Rise tDOH Data Output Hold After CLK Rise [20, 21, 22] 6.5 2.0 8.5 2.0 ns tCLZ Clock to Low-Z tCHZ Clock to High-Z[20, 21, 22] 4.0 5.0 ns tOEV OE LOW to Output Valid 3.2 3.
PAGE 22
CY7C1371D CY7C1373D Switching Waveforms Read/Write Waveforms[25, 26, 27] 1 2 3 t CYC 4 5 6 7 8 9 A5 A6 A7 10 CLK t CENS t CENH t CES t CEH t CH t CL CEN CE ADV/LD WE BW X A1 ADDRESS t AS A2 A4 A3 t CDV t AH t DOH t CLZ DQ D(A1) t DS D(A2) Q(A3) D(A2+1) t OEV Q(A4+1) Q(A4) t OELZ W RITE D(A1) W RITE D(A2) D(A5) Q(A6) D(A7) W RITE D(A7) DESELECT t OEHZ t DH OE COM M AND t CHZ BURST W RITE D(A2+1) READ Q(A3) READ Q(A4) DON’T CARE BURST READ Q(A4+1) t DOH
PAGE 23
CY7C1371D CY7C1373D Switching Waveforms (continued) NOP, STALL AND DESELECT Cycles[25, 26, 28] 1 2 A1 A2 3 4 5 A3 A4 6 7 8 9 10 CLK CEN CE ADV/LD WE BW [A:D] ADDRESS A5 t CHZ D(A1) DQ Q(A2) Q(A3) D(A4) Q(A5) t DOH COMMAND WRITE D(A1) READ Q(A2) STALL READ Q(A3) WRITE D(A4) DON’T CARE STALL NOP READ Q(A5) DESELECT CONTINUE DESELECT UNDEFINED Note: 28. The IGNORE CLOCK EDGE or STALL cycle (Clock 3) illustrates CEN being used to create a pause.
PAGE 24
CY7C1371D CY7C1373D Switching Waveforms (continued) ZZ Mode Timing[29, 30] CLK t ZZ I t ZZREC ZZ t ZZI SUPPLY I DDZZ t RZZI ALL INPUTS (except ZZ) Outputs (Q) DESELECT or READ Only High-Z DON’T CARE Notes: 29. Device must be deselected when entering ZZ mode. See truth table for all possible signal conditions to deselect the device. 30. DQs are in high-Z when exiting ZZ sleep mode. Document #: 38-05556 Rev.
PAGE 25
CY7C1371D CY7C1373D Ordering Information Not all of the speed, package and temperature ranges are available. Please contact your local sales representative or visit www.cypress.com for actual products offered. Speed (MHz) 133 Ordering Code CY7C1371D-133AXC Package Diagram Operating Range Part and Package Type 51-85050 100-Pin Thin Quad Flat Pack (14 x 20 x 1.4 mm) Pb-Free Commercial CY7C1373D-133AXC CY7C1371D-133BGC 51-85115 119-Ball Grid Array (14 x 22 x 2.
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CY7C1371D CY7C1373D Package Diagrams Figure 1. 100-Pin Thin Plastic Quad Flatpack (14 x 20 x 1.4 mm), 51-85050 16.00±0.20 1.40±0.05 14.00±0.10 100 81 80 1 20.00±0.10 22.00±0.20 0.30±0.08 0.65 TYP. 30 12°±1° (8X) SEE DETAIL A 51 31 50 0.20 MAX. 0.10 1.60 MAX. R 0.08 MIN. 0.20 MAX. 0° MIN. SEATING PLANE STAND-OFF 0.05 MIN. 0.15 MAX. 0.25 NOTE: 1. JEDEC STD REF MS-026 GAUGE PLANE 0°-7° R 0.08 MIN. 0.20 MAX. 2.
PAGE 27
CY7C1371D CY7C1373D Package Diagrams (continued) Figure 2. 119-Ball BGA (14 x 22 x 2.4 mm) (51-85115) Ø0.05 M C Ø0.25 M C A B A1 CORNER Ø0.75±0.15(119X) Ø1.00(3X) REF. 1 2 3 4 5 6 7 7 6 5 4 3 2 1 A A B B C D 1.27 C D E E F F H 19.50 J K L 20.32 G H 22.00±0.20 G J K L M 10.16 M N P N P R R T T U U 1.27 0.70 REF. A 3.81 7.62 30° TYP. 14.00±0.20 0.15(4X) 0.15 C 2.40 MAX. B 0.90±0.05 0.25 C 12.00 C Document #: 38-05556 Rev. *F 0.60±0.10 0.
PAGE 28
CY7C1371D CY7C1373D Package Diagrams (continued) Figure 3. 165-Ball FBGA (13 x 15 x 1.4 mm) (51-85180) BOTTOM VIEW PIN 1 CORNER TOP VIEW Ø0.05 M C Ø0.25 M C A B PIN 1 CORNER Ø0.50 -0.06 (165X) +0.14 1 2 3 4 5 6 7 8 9 10 11 11 9 8 7 6 5 4 3 2 1 A B B C C 1.00 A D D E F F G G H J 14.00 E 15.00±0.10 15.00±0.10 10 H J K L L 7.00 K M M N N P P R R A A 1.00 5.00 10.00 B B 13.00±0.10 13.00±0.10 1.40 MAX. 0.15 C 0.53±0.05 0.25 C 0.
PAGE 29
CY7C1371D CY7C1373D Document History Page Document Title: CY7C1371D/CY7C1373D 18-Mbit (512K x 36/1 Mbit x 18) flow through SRAM with NoBL™ Architecture Document Number: 38-05556 REV. ECN NO. Issue Date Orig. of Change Description of Change ** 254513 See ECN RKF New data sheet *A 288531 See ECN SYT Edited description under “IEEE 1149.1 Serial Boundary Scan (JTAG)” for non-compliance with 1149.