Pipelined SRAM Specification Sheet

ManualsBrandsCypress ManualsComputer HardwareNoBL CY7C1472V33

72-Mbit (2M x 36/4M x 18/1M x 72)

elined SRAM with NoBL™ Architecture

CY7C1470V33

CY7C1472V33

CY7C1474V33

Cypress Semiconductor Corporation • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600

Document #: 38-05289 Rev. *I Revised June 20, 2006

Features

• Pin-compatible and functionally equivalent to ZBT™

• Supports 250-MHz bus operations with zero wait states

— Available speed grades are 250, 200 and 167 MHz

• Internally self-timed output buffer control to eliminate

the need to use asynchronous OE

• Fully registered (inputs and outputs) for pipelined

operation

• Byte Write capability

• Single 3.3V power supply

• 3.3V/2.5V I/O power supply

• Fast clock-to-output time

— 3.0 ns (for 250-MHz device)

• Clock Enable (CEN

) pin to suspend operation

• Synchronous self-timed writes

• CY7C1470V33, CY7C1472V33 available in

JEDEC-standard lead-free 100-pin TQFP, lead-free and

non-lead-free 165-ball FBGA package. CY7C1474V33

available in lead-free and non-lead-free 209 ball FBGA

package

• IEEE 1149.1 JTAG Boundary Scan compatible

• Burst capability—linear or interleaved burst order

• “ZZ” Sleep Mode option and Stop Clock option

Functional Description

The CY7C1470V33, CY7C1472V33, and CY7C1474V33 are

3.3V, 2M x 36/4M x 18/1M x 72 Synchronous pipelined burst

SRAMs with No Bus Latency™ (NoBL™) logic, respectively.

They are designed to support unlimited true back-to-back

Read/Write operations with no wait states. The

CY7C1470V33, CY7C1472V33, and CY7C1474V33 are

equipped with the advanced (NoBL) logic required to enable

consecutive Read/Write operations with data being trans-

ferred on every clock cycle. This feature dramatically improves

the throughput of data in systems that require frequent

Write/Read transitions. The CY7C1470V33, CY7C1472V33,

and CY7C1474V33 are pin compatible and functionally equiv-

alent to ZBT devices.

All synchronous inputs pass through input registers controlled

by the rising edge of the clock. All data outputs pass through

output registers controlled by the rising edge of the clock. The

clock input is qualified by the Clock Enable (CEN

) signal,

which when deasserted suspends operation and extends the

previous clock cycle.

Write operations are controlled by the Byte Write Selects

(BW

–BW

for CY7C1474V33, BW

–BW

for CY7C1470V33

and BW

–BW

for CY7C1472V33) and a Write Enable (WE)

input. All writes are conducted with on-chip synchronous

self-timed write circuitry.

Three synchronous Chip Enables (CE

, CE

) and an

asynchronous Output Enable (OE

) provide for easy bank

selection and output tri-state control. In order to avoid bus

contention, the output drivers are synchronously tri-stated

during the data portion of a write sequence.

Logic Block Diagram-CY7C1470V33 (2M x 36)

A0, A1, A

MODE

CE1

CE2

CE3

READ LOGIC

DQs

DQP

MEMORY

ARRAY

INPUT

ADDRESS

WRITE ADDRESS

WRITE REGISTRY

AND DATA COHERENCY

CONTROL LOGIC

BURST

LOGIC

A0'

A1'

ADV/LD

INPUT

WRITE

DRIVERS

SLEEP

CONTROL

[+] Feedback

Summary of content (29 pages)

PAGE 1
CY7C1470V33 CY7C1472V33 CY7C1474V33 72-Mbit (2M x 36/4M x 18/1M x 72) Pipelined SRAM with NoBL™ Architecture Features Functional Description • Pin-compatible and functionally equivalent to ZBT™ • Supports 250-MHz bus operations with zero wait states — Available speed grades are 250, 200 and 167 MHz • Internally self-timed output buffer control to eliminate the need to use asynchronous OE • Fully registered (inputs and outputs) for pipelined operation • Byte Write capability • Single 3.
PAGE 2
CY7C1470V33 CY7C1472V33 CY7C1474V33 Logic Block Diagram-CY7C1472V33 (4M x 18) ADDRESS REGISTER 0 A0, A1, A A1 A1' D1 Q1 A0 A0' BURST D0 Q0 LOGIC MODE CLK CEN ADV/LD C C WRITE ADDRESS REGISTER 1 WRITE ADDRESS REGISTER 2 ADV/LD WRITE REGISTRY AND DATA COHERENCY CONTROL LOGIC BWa WRITE DRIVERS O U T P U T S E N S E MEMORY ARRAY R E G I S T E R S A M P S BWb WE O U T P U T D A T A B U F F E R S S T E E R I N G E E INPUT REGISTER 1 E OE CE1 CE2 CE3 DQs DQPa DQPb INPUT REGISTER 0 E READ
PAGE 3
CY7C1470V33 CY7C1472V33 CY7C1474V33 Pin Configurations 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 DQPb DQb DQb VDDQ VSS NC NC NC VDDQ VSS NC NC DQb DQb VSS VDDQ CY7C1472V33 (4M x 18) 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 Document #: 38-05289 Rev.
PAGE 4
CY7C1470V33 CY7C1472V33 CY7C1474V33 Pin Configurations (continued) 165-ball FBGA (15 x 17 x 1.
PAGE 5
CY7C1470V33 CY7C1472V33 CY7C1474V33 Pin Configurations (continued) 209-ball FBGA (14 x 22 x 1.
PAGE 6
CY7C1470V33 CY7C1472V33 CY7C1474V33 Pin Definitions I/O Type Pin Description A0 A1 A Pin Name InputSynchronous Address Inputs used to select one of the address locations. Sampled at the rising edge of the CLK. BWa BWb BWc BWd BWe BWf BWg BWh InputSynchronous Byte Write Select Inputs, active LOW. Qualified with WE to conduct writes to the SRAM. Sampled on the rising edge of CLK.
PAGE 7
CY7C1470V33 CY7C1472V33 CY7C1474V33 Pin Definitions (continued) Pin Name TMS I/O Type Test Mode Select This pin controls the Test Access Port state machine. Sampled on the rising edge of TCK. Synchronous TCK JTAG Clock VDD Power Supply VDDQ Pin Description Clock input to the JTAG circuitry. Power supply inputs to the core of the device. I/O Power Supply Power supply for the I/O circuitry. VSS Ground NC – No connects. This pin is not connected to the die.
PAGE 8
CY7C1470V33 CY7C1472V33 CY7C1474V33 On the next clock rise the data presented to DQ and DQP for CY7C1474V33, (DQa,b,c,d,e,f,g,h/DQPa,b,c,d,e,f,g,h DQa,b,c,d/DQPa,b,c,d for CY7C1470V33 & DQa,b/DQPa,b for CY7C1472V33) (or a subset for byte write operations, see Write Cycle Description table for details) inputs is latched into the device and the write is complete.
PAGE 9
CY7C1470V33 CY7C1472V33 CY7C1474V33 Truth Table[1, 2, 3, 4, 5, 6, 7] Operation Address Used CE ZZ ADV/LD WE BWx OE CEN CLK DQ Deselect Cycle None H L L X X X L L-H Tri-State Continue Deselect Cycle None X L H X X X L L-H Tri-State Read Cycle (Begin Burst) External L L L H X L L L-H Data Out (Q) Read Cycle (Continue Burst) Next X L H X X L L L-H Data Out (Q) NOP/Dummy Read (Begin Burst) External L L L H X H L L-H Tri-State Dummy Read (Continue
PAGE 10
CY7C1470V33 CY7C1472V33 CY7C1474V33 Partial Write Cycle Description[1, 2, 3, 8] Function (CY7C1470V33) WE BWd BWc BWb BWa Read H X X X X Write – No bytes written L H H H H Write Byte a – (DQa and DQPa) L H H H L Write Byte b – (DQb and DQPb) L H H L H Write Bytes b, a L H H L L Write Byte c – (DQc and DQPc) L H L H H Write Bytes c, a L H L H L Write Bytes c, b L H L L H Write Bytes c, b, a L H L L L Write Byte d – (DQd and DQPd) L L H H H Wri
PAGE 11
CY7C1470V33 CY7C1472V33 CY7C1474V33 IEEE 1149.1 Serial Boundary Scan (JTAG) Test MODE SELECT (TMS) The CY7C1470V33, CY7C1472V33, and CY7C1474V33 incorporates a serial boundary scan test access port (TAP). This port operates in accordance with IEEE Standard 1149.1-1990 but does not have the set of functions required for full 1149.1 compliance. These functions from the IEEE specification are excluded because their inclusion places an added delay in the critical speed path of the SRAM.
PAGE 12
CY7C1470V33 CY7C1472V33 CY7C1474V33 Instruction Register Three-bit instructions can be serially loaded into the instruction register. This register is loaded when it is placed between the TDI and TDO balls as shown in the Tap Controller Block Diagram. Upon power-up, the instruction register is loaded with the IDCODE instruction. It is also loaded with the IDCODE instruction if the controller is placed in a reset state as described in the previous section.
PAGE 13
CY7C1470V33 CY7C1472V33 CY7C1474V33 BYPASS possible to capture all other signals and simply ignore the value of the CLK captured in the boundary scan register. When the BYPASS instruction is loaded in the instruction register and the TAP is placed in a Shift-DR state, the bypass register is placed between the TDI and TDO balls. The advantage of the BYPASS instruction is that it shortens the boundary scan path when multiple devices are connected together on a board.
PAGE 14
CY7C1470V33 CY7C1472V33 CY7C1474V33 3.3V TAP AC Test Conditions 2.5V TAP AC Test Conditions Input pulse levels ................................................ VSS to 3.3V Input pulse levels................................................. VSS to 2.5V Input rise and fall times ................................................... 1 ns Input rise and fall time .....................................................1 ns Input timing reference levels ...........................................1.
PAGE 15
CY7C1470V33 CY7C1472V33 CY7C1474V33 Identification Register Definitions Instruction Field CY7C1470V33 (2M x 36) CY7C1472V33 (4M x 18) CY7C1474V33 (1M x 72) Description Revision Number (31:29) 000 000 000 Device Depth (28:24)[12] 01011 01011 01011 001000 001000 001000 Defines memory type and architecture Defines width and density Architecture/Memory Type(23:18) Bus Width/Density(17:12) 100100 010100 110100 Cypress JEDEC ID Code (11:1) 00000110100 00000110100 00000110100 1 1 1 ID R
PAGE 16
CY7C1470V33 CY7C1472V33 CY7C1474V33 Boundary Scan Exit Order (2M x 36) Bit # 165-Ball ID Bit # 165-Ball ID Bit # 165-Ball ID Bit # 165-Ball ID 1 C1 21 R3 41 J11 61 B7 2 D1 22 P2 42 K10 62 B6 3 E1 23 R4 43 J10 63 A6 4 D2 24 P6 44 H11 64 B5 5 E2 25 R6 45 G11 65 A5 6 F1 26 R8 46 F11 66 A4 7 G1 27 P3 47 E11 67 B4 8 F2 28 P4 48 D10 68 B3 9 G2 29 P8 49 D11 69 A3 10 J1 30 P9 50 C11 70 A2 11 K1 31 P10 51 G10 71 B2 12 L1
PAGE 17
CY7C1470V33 CY7C1472V33 CY7C1474V33 Boundary Scan Exit Order (1M x 72) Bit # 209-Ball ID Bit # 209-Ball ID Bit # 209-Ball ID Bit # 209-Ball ID 1 A1 29 T1 57 U10 85 B11 2 A2 30 T2 58 T11 86 B10 3 B1 31 U1 59 T10 87 A11 4 B2 32 U2 60 R11 88 A10 5 C1 33 V1 61 R10 89 A7 6 C2 34 V2 62 P11 90 A5 7 D1 35 W1 63 P10 91 A9 8 D2 36 W2 64 N11 92 U8 9 E1 37 T6 65 N10 93 A6 10 E2 38 V3 66 M11 94 D6 11 F1 39 V4 67 M10 95 K6 12
PAGE 18
CY7C1470V33 CY7C1472V33 CY7C1474V33 Maximum Ratings Current into Outputs (LOW)......................................... 20 mA (Above which the useful life may be impaired. For user guidelines, not tested.) Storage Temperature ................................. –65°C to +150°C Ambient Temperature with Power Applied............................................. –55°C to +125°C Static Discharge Voltage.......................................... > 2001V (per MIL-STD-883, Method 3015) Latch-up Current...........
PAGE 19
CY7C1470V33 CY7C1472V33 CY7C1474V33 Capacitance[15] Parameter Description 100 TQFP Max. Test Conditions CADDRESS Address Input Capacitance CDATA Data Input Capacitance CCTRL Control Input Capacitance CCLK Clock Input Capacitance CI/O Input/Output Capacitance TA = 25°C, f = 1 MHz, VDD = 3.3V VDDQ = 2.5V 165 FBGA 209 FBGA Max. Max.
PAGE 20
CY7C1470V33 CY7C1472V33 CY7C1474V33 Switching Characteristics Over the Operating Range [16, 17] –250 Parameter tPower [18] –200 Max. Min. –167 Description Min. Max. Min. Max. Unit VCC (typical) to the First Access Read or Write 1 1 1 ms 4.0 5.0 6.0 ns Clock tCYC Clock Cycle Time FMAX Maximum Operating Frequency tCH Clock HIGH 2.0 2.0 2.2 ns tCL Clock LOW 2.0 2.0 2.
PAGE 21
CY7C1470V33 CY7C1472V33 CY7C1474V33 Switching Waveforms Read/Write/Timing[22, 23, 24] 1 2 3 t CYC 4 5 6 A3 A4 7 8 9 A5 A6 A7 10 CLK tCENS tCENH tCH tCL CEN tCES tCEH CE ADV/LD WE BWx A1 ADDRESS A2 tCO tAS tDS tAH Data tDH D(A1) tCLZ D(A2) D(A2+1) tDOH Q(A3) tOEV Q(A4) tCHZ Q(A4+1) D(A5) Q(A6) In-Out (DQ) tOEHZ tDOH tOELZ OE WRITE D(A1) WRITE D(A2) BURST WRITE D(A2+1) READ Q(A3) READ Q(A4) DON’T CARE BURST READ Q(A4+1) WRITE D(A5) READ Q(A6) WRITE D(A7) D
PAGE 22
CY7C1470V33 CY7C1472V33 CY7C1474V33 Switching Waveforms (continued) NOP, STALL and DESELECT Cycles[22, 23, 25] 1 2 A1 A2 3 4 5 A3 A4 6 7 8 9 10 CLK CEN CE ADV/LD WE BWx ADDRESS A5 tCHZ D(A1) Data Q(A2) D(A4) Q(A3) Q(A5) In-Out (DQ) WRITE D(A1) READ Q(A2) STALL READ Q(A3) WRITE D(A4) STALL DON’T CARE NOP READ Q(A5) DESELECT CONTINUE DESELECT UNDEFINED ZZ Mode Timing[26, 27] CLK t ZZ ZZ I t ZZREC t ZZI SUPPLY I DDZZ t RZZI ALL INPUTS (except ZZ) Outputs (Q) DESELECT
PAGE 23
CY7C1470V33 CY7C1472V33 CY7C1474V33 Ordering Information Not all of the speed, package and temperature ranges are available. Please contact your local sales representative or visit www.cypress.com for actual products offered. Speed (MHz) 167 Ordering Code CY7C1470V33-167AXC Package Diagram Operating Range Part and Package Type 51-85050 100-Pin Thin Quad Flat Pack (14 x 20 x 1.4 mm) Lead-Free Commercial CY7C1472V33-167AXC CY7C1470V33-167BZC 51-85165 165-ball Fine-Pitch Ball Grid Array (15 x 17 x 1.
PAGE 24
CY7C1470V33 CY7C1472V33 CY7C1474V33 Ordering Information (continued) Not all of the speed, package and temperature ranges are available. Please contact your local sales representative or visit www.cypress.com for actual products offered. Speed (MHz) 250 Ordering Code CY7C1470V33-250AXC Package Diagram Operating Range Part and Package Type 51-85050 100-Pin Thin Quad Flat Pack (14 x 20 x 1.
PAGE 25
CY7C1470V33 CY7C1472V33 CY7C1474V33 Package Diagrams 100-Pin Thin Plastic Quad Flatpack (14 x 20 x 1.4 mm) (51-85050) 16.00±0.20 1.40±0.05 14.00±0.10 100 81 80 1 20.00±0.10 22.00±0.20 0.30±0.08 0.65 TYP. 30 12°±1° (8X) SEE DETAIL A 51 31 50 0.20 MAX. 0.10 1.60 MAX. R 0.08 MIN. 0.20 MAX. 0° MIN. SEATING PLANE STAND-OFF 0.05 MIN. 0.15 MAX. 0.25 NOTE: 1. JEDEC STD REF MS-026 GAUGE PLANE 0°-7° R 0.08 MIN. 0.20 MAX. 2.
PAGE 26
CY7C1470V33 CY7C1472V33 CY7C1474V33 Package Diagrams (continued) 165-ball FBGA (15 x 17 x 1.4 mm) (51-85165) PIN 1 CORNER BOTTOM VIEW TOP VIEW Ø0.05 M C PIN 1 CORNER Ø0.25 M C A B Ø0.45±0.05(165X) 1 2 3 4 5 6 7 8 9 10 11 11 10 9 8 7 6 5 4 3 1 2 A B B C C 1.00 A D D F F G G H J 14.00 E 17.00±0.10 E H J K L L 7.00 K M M N N P P R R A 1.00 5.00 0.35 0.15 C +0.05 -0.10 0.53±0.05 0.25 C 10.00 B 15.00±0.10 0.15(4X) SEATING PLANE 1.40 MAX. 0.
PAGE 27
CY7C1470V33 CY7C1472V33 CY7C1474V33 Package Diagrams (continued) 209-ball FBGA (14 x 22 x 1.76 mm) (51-85167) 51-85167-** NoBL and No Bus Latency are trademarks of Cypress Semiconductor Corporation. ZBT is a trademark of Integrated Device Technology. All product and company names mentioned in this document are the trademarks of their respective holders. Document #: 38-05289 Rev. *I Page 27 of 29 © Cypress Semiconductor Corporation, 2006.
PAGE 28
CY7C1470V33 CY7C1472V33 CY7C1474V33 Document History Page Document Title: CY7C1470V33/CY7C1472V33/CY7C1474V33 72-Mbit (2M x 36/4M x 18/1M x 72) Pipelined SRAM with NoBL™ Architecture Document Number: 38-05289 REV. ECN No. Issue Date Orig. of Change Description of Change ** 114676 08/06/02 PKS New Data Sheet *A 121520 01/27/03 CJM Updated features for package offering Removed 300-MHz offering Changed tCO, tEOV, tCHZ, tEOHZ from 2.4 ns to 2.6 ns (250 MHz), tDOH, tCLZ from 0.8 ns to 1.
PAGE 29
CY7C1470V33 CY7C1472V33 CY7C1474V33 Document Title: CY7C1470V33/CY7C1472V33/CY7C1474V33 72-Mbit (2M x 36/4M x 18/1M x 72) Pipelined SRAM with NoBL™ Architecture Document Number: 38-05289 REV. ECN No. Issue Date Orig.