Pipelined SRAM with NoBL Specifiation Sheet

ManualsBrandsCypress ManualsComputer HardwarePerform CY7C1356C

9-Mbit (256K x 36/512K x 18)

elined SRAM with NoBL™ Architecture

CY7C1354C

CY7C1356C

Cypress Semiconductor Corporation • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600

Document #: 38-05538 Rev. *G Revised September 14, 2006

Features

• Pin-compatible and functionally equivalent to ZBT™

• Supports 250-MHz bus operations with zero wait states

— Available speed grades are 250, 200, and 166 MHz

• Internally self-timed output buffer control to eliminate

the need to use asynchronous OE

• Fully registered (inputs and outputs) for pipelined

operation

• Byte Write capability

• Single 3.3V power supply (V

)

• 3.3V or 2.5V I/O power supply (V

DDQ

)

• Fast clock-to-output times

— 2.8 ns (for 250-MHz device)

• Clock Enable (CEN

) pin to suspend operation

• Synchronous self-timed writes

• Available in lead-free 100-Pin TQFP package, lead-free

and non lead-free 119-Ball BGA package and 165-Ball

FBGA package

• IEEE 1149.1 JTAG-Compatible Boundary Scan

• Burst capability–linear or interleaved burst order

• “ZZ” Sleep Mode option and Stop Clock option

Functional Description

[1]

The CY7C1354C and CY7C1356C are 3.3V, 256K x 36 and

512K x 18 Synchronous pipelined burst SRAMs with No Bus

Latency™ (NoBL™) logic, respectively. They are designed to

support unlimited true back-to-back Read/Write operations

with no wait states. The CY7C1354C and CY7C1356C are

equipped with the advanced (NoBL) logic required to enable

consecutive Read/Write operations with data being trans-

ferred on every clock cycle. This feature dramatically improves

the throughput of data in systems that require frequent

Write/Read transitions. The CY7C1354C and CY7C1356C are

pin compatible and functionally equivalent to ZBT devices.

All synchronous inputs pass through input registers controlled

by the rising edge of the clock. All data outputs pass through

output registers controlled by the rising edge of the clock. The

clock input is qualified by the Clock Enable (CEN

) signal,

which when deasserted suspends operation and extends the

previous clock cycle.

Write operations are controlled by the Byte Write Selects

(BW

–BW

for CY7C1354C and BW

–BW

for CY7C1356C)

and a Write Enable (WE

) input. All writes are conducted with

on-chip synchronous self-timed write circuitry.

Three synchronous Chip Enables (CE

, CE

) and an

asynchronous Output Enable (OE

) provide for easy bank

selection and output tri-state control. In order to avoid bus

contention, the output drivers are synchronously tri-stated

during the data portion of a write sequence.

Note:

1. For best-practices recommendations, please refer to the Cypress application note System Design Guidelines on www.cypress.com.

A0, A1, A

MODE

CE1

CE2

CE3

READ LOGIC

DQs

DQP

MEMORY

ARRAY

INPUT

ADDRESS

WRITE ADDRESS

WRITE REGISTRY

AND DATA COHERENCY

CONTROL LOGIC

BURST

LOGIC

A0'

A1'

ADV/LD

INPUT

CLK

WRITE

DRIVERS

SLEEP

CONTROL

Logic Block Diagram–CY7C1354C (256K x 36)

[+] Feedback

Summary of content (28 pages)

PAGE 1
CY7C1354C CY7C1356C 9-Mbit (256K x 36/512K x 18) Pipelined SRAM with NoBL™ Architecture Functional Description[1] Features • Pin-compatible and functionally equivalent to ZBT™ • Supports 250-MHz bus operations with zero wait states — Available speed grades are 250, 200, and 166 MHz • Internally self-timed output buffer control to eliminate the need to use asynchronous OE • Fully registered (inputs and outputs) for pipelined operation • Byte Write capability • Single 3.
PAGE 2
CY7C1354C CY7C1356C Logic Block Diagram–CY7C1356C (512K x 18) A0, A1, A ADDRESS REGISTER 0 A1 A1' D1 Q1 A0 A0' BURST D0 Q0 LOGIC MODE CLK CEN ADV/LD C C WRITE ADDRESS REGISTER 1 WRITE ADDRESS REGISTER 2 ADV/LD BWa WRITE REGISTRY AND DATA COHERENCY CONTROL LOGIC WRITE DRIVERS MEMORY ARRAY BWb WE S E N S E A M P S O U T P U T R E G I S T E R S D A T A S T E E R I N G E INPUT REGISTER 1 E OE CE1 CE2 CE3 ZZ O U T P U T B U F F E R S DQs DQPa DQPb E INPUT REGISTER 0 E READ LOGIC Sleep Cont
PAGE 3
CY7C1354C CY7C1356C Pin Configurations 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 DQPb DQb DQb VDDQ VSS NC NC NC VDDQ VSS NC NC DQb DQb VSS VDDQ CY7C1356C (512K × 18) 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 A NC NC VDDQ VSS NC DQPa DQa DQa VSS VDDQ DQa DQa VSS NC VDD ZZ DQa DQa VDDQ VSS DQa DQa NC NC VSS VDDQ NC NC NC A A A A A A A NC(36) NC(72) VSS VDD NC(288) NC(144) A A A A A A A NC(36) 31 32 33 34 35 36 37 38 39 40 41 42 43
PAGE 4
CY7C1354C CY7C1356C Pin Configurations (continued) 119-Ball BGA Pinout CY7C1354C (256K × 36) 1 2 3 4 5 6 7 A VDDQ A A NC/18M A A VDDQ B C D E F G H J K L M N P NC/576M NC/1G DQc CE2 A DQPc A A VSS ADV/LD VDD NC A A VSS CE3 A DQPb NC NC DQb CE1 VSS DQb DQb OE A VSS DQb VDDQ BWb DQb DQb WE VDD VSS NC DQb VDD DQb VDDQ CLK NC VSS BWa DQa DQa DQa DQa R T U DQc DQc VSS VDDQ DQc VSS DQc DQc DQc VDDQ DQc VDD BWc VSS NC DQd DQd DQd DQd BWd VDDQ DQd VSS DQa
PAGE 5
CY7C1354C CY7C1356C Pin Configurations (continued) 165-Ball FBGA Pinout CY7C1354C (256K × 36) 5 6 7 1 2 3 4 8 9 10 11 A B C D E F G H J K L M N P NC/576M A CE1 BWc BWb CE3 ADV/LD A A NC CLK CEN WE NC/1G A NC DQc CE2 DQPc DQc VDDQ VDDQ BWd VSS VDD BWa VSS OE NC/18M A NC VSS VSS VSS VDD VDDQ VSS VSS VSS VDDQ NC DQb DQPb DQb DQc DQc VDDQ VDD VSS VSS VSS VDD VDDQ DQb DQb R MODE DQc DQc VDDQ VDD VSS VSS VSS VDD VDDQ DQb DQb DQc NC DQd DQc NC DQd
PAGE 6
CY7C1354C CY7C1356C Pin Definitions Pin Name I/O Type Pin Description A0, A1 A InputSynchronous Address Inputs used to select one of the address locations. Sampled at the rising edge of the CLK. BWa,BWb, BWc,BWd, InputSynchronous Byte Write Select Inputs, active LOW. Qualified with WE to conduct writes to the SRAM. Sampled on the rising edge of CLK. BWa controls DQa and DQPa, BWb controls DQb and DQPb, BWc controls DQc and DQPc, BWd controls DQd and DQPd.
PAGE 7
CY7C1354C CY7C1356C Pin Definitions (continued) Pin Name I/O Type Pin Description NC – No connects. This pin is not connected to the die. NC (18, 36, 72, 144, 288, 576, 1G) – These pins are not connected. They will be used for expansion to the 18M, 36M, 72M, 144M 288M, 576M and 1G densities. ZZ InputZZ “sleep” Input. This active HIGH input places the device in a non-time-critical “sleep” Asynchronous condition with data integrity preserved.
PAGE 8
CY7C1354C CY7C1356C mode. While in this mode, data integrity is guaranteed. Accesses pending when entering the “sleep” mode are not considered valid nor is the completion of the operation guaranteed. The device must be deselected prior to entering the “sleep” mode. CE1, CE2, and CE3, must remain inactive for the duration of tZZREC after the ZZ input returns LOW. Because the CY7C1354C and CY7C1356C are common I/O devices, data should not be driven into the device while the outputs are active.
PAGE 9
CY7C1354C CY7C1356C Truth Table[2, 3, 4, 5, 6, 7, 8] Operation Address Used CE ZZ ADV/LD WE BWx OE CEN CLK DQ NOP/WRITE ABORT (Begin Burst) None L L L L H X L L-H Tri-State WRITE ABORT (Continue Burst) Next X L H X H X L L-H Tri-State IGNORE CLOCK EDGE (Stall) SLEEP MODE Current X L X X X X H L-H - None X H X X X X X X Tri-State Partial Write Cycle Description[2, 3, 4, 9] Function (CY7C1354C) Read WE H BWd X BWc X BWb X BWa X Write –No bytes written
PAGE 10
CY7C1354C CY7C1356C IEEE 1149.1 Serial Boundary Scan (JTAG) Test MODE SELECT (TMS) The CY7C1354C/CY7C1356C incorporates a serial boundary scan test access port (TAP) in the BGA package only. The TQFP package does not offer this functionality. This part operates in accordance with IEEE Standard 1149.1-1900, but doesn’t have the set of functions required for full 1149.1 compliance.
PAGE 11
CY7C1354C CY7C1356C TDI and TDO balls as shown in the Tap Controller Block Diagram. Upon power-up, the instruction register is loaded with the IDCODE instruction. It is also loaded with the IDCODE instruction if the controller is placed in a reset state as described in the previous section. through the instruction register through the TDI and TDO balls. To execute the instruction once it is shifted in, the TAP controller needs to be moved into the Update-IR state.
PAGE 12
CY7C1354C CY7C1356C register is placed between the TDI and TDO balls. The advantage of the BYPASS instruction is that it shortens the boundary scan path when multiple devices are connected together on a board. PRELOAD allows an initial data pattern to be placed at the latched parallel outputs of the boundary scan register cells prior to the selection of another boundary scan test operation.
PAGE 13
CY7C1354C CY7C1356C 3.3V TAP AC Test Conditions 2.5V TAP AC Test Conditions Input pulse levels ................................................ VSS to 3.3V Input pulse levels................................................. VSS to 2.5V Input rise and fall times ................................................... 1 ns Input rise and fall time .....................................................1 ns Input timing reference levels ...........................................1.
PAGE 14
CY7C1354C CY7C1356C Scan Register Sizes Register Name Instruction Bit Size (x36) Bit Size (x18) 3 3 Bypass 1 1 ID 32 32 Boundary Scan Order (119-ball BGA package) 69 69 Boundary Scan Order (165-ball FBGA package) 69 69 Identification Codes Instruction Code Description EXTEST 000 Captures the Input/Output ring contents. Places the boundary scan register between the TDI and TDO. Forces all SRAM outputs to High-Z state.
PAGE 15
CY7C1354C CY7C1356C Boundary Scan Exit Order (256K × 36) Boundary Scan Exit Order (256K × 36) (continued) Bit # 119-ball ID 165-ball ID Bit # 119-ball ID 165-ball ID 1 K4 B6 44 L2 K2 2 H4 B7 45 K1 J2 3 M4 A7 46 N2 M2 4 F4 B8 47 N1 M1 5 B4 A8 48 M2 L1 6 G4 A9 49 L1 K1 7 C3 B10 50 K2 J1 8 B3 A10 51 9 D6 C11 Not Bonded (Preset to 1) Not Bonded (Preset to 1) 10 H7 E10 52 H1 G2 G2 F2 11 G6 F10 53 12 E6 G10 54 E2 E2 D1 D2 13 D7 D10
PAGE 16
CY7C1354C CY7C1356C Boundary Scan Exit Order (512K × 18) Boundary Scan Exit Order (512K × 18) (continued) Bit # 119-ball ID 165-ball ID Bit # 119-ball ID 165-ball ID 1 K4 B6 39 T3 R3 2 H4 B7 40 R2 P3 3 M4 A7 41 R3 R1 42 Not Bonded (Preset to 0) Not Bonded (Preset to 0) 43 Not Bonded (Preset to 0) Not Bonded (Preset to 0) 44 Not Bonded (Preset to 0) Not Bonded (Preset to 0) Not Bonded (Preset to 0) Not Bonded (Preset to 0) 4 F4 B8 5 B4 A8 6 G4 A9 7 C3 B10 8 B
PAGE 17
CY7C1354C CY7C1356C Maximum Ratings DC Input Voltage ................................... –0.5V to VDD + 0.5V (Above which the useful life may be impaired. For user guidelines, not tested.) Storage Temperature ................................. –65°C to +150°C Ambient Temperature with Power Applied............................................. –55°C to +125°C Current into Outputs (LOW)......................................... 20 mA Static Discharge Voltage...........................................
PAGE 18
CY7C1354C CY7C1356C Capacitance[16] Parameter Test Conditions 100 TQFP Max. TA = 25°C, f = 1 MHz, VDD = 3.3V VDDQ = 2.5V 5 5 5 pF 5 5 5 pF 5 7 7 pF Description CIN Input Capacitance CCLK Clock Input Capacitance CI/O Input/Output Capacitance 119 BGA Max. 165 FBGA Max.
PAGE 19
CY7C1354C CY7C1356C Switching Characteristics Over the Operating Range [18, 19] –250 –200 Parameter Description Min. [17] VCC (typical) to the First Access Read or Write 1 1 1 ms 4.0 5 6 ns tPower Max. Min. –166 Max. Min. Max. Unit Clock tCYC Clock Cycle Time FMAX Maximum Operating Frequency tCH Clock HIGH 1.8 2.0 2.4 ns tCL Clock LOW 1.8 2.0 2.4 ns tEOV OE LOW to Output Valid tCLZ [20, 21, 22] 250 200 2.8 Clock to Low-Z 1.25 166 3.2 1.5 3.5 1.
PAGE 20
CY7C1354C CY7C1356C Switching Waveforms Read/Write Timing[23, 24, 25] 1 2 3 t CYC 4 5 6 A3 A4 7 8 9 A5 A6 A7 10 CLK tCENS tCENH tCH tCL CEN tCES tCEH CE ADV/LD WE BWX A1 ADDRESS A2 tCO tAS tDS tAH Data tDH D(A1) tCLZ D(A2) D(A2+1) tDOH Q(A3) tOEV Q(A4) tCHZ Q(A4+1) D(A5) Q(A6) n-Out (DQ) tOEHZ tDOH tOELZ OE WRITE D(A1) WRITE D(A2) BURST WRITE D(A2+1) READ Q(A3) READ Q(A4) DON’T CARE BURST READ Q(A4+1) WRITE D(A5) READ Q(A6) WRITE D(A7) DESELECT UNDEFINE
PAGE 21
CY7C1354C CY7C1356C Switching Waveforms (continued) NOP,STALL and DESELECT Cycles[23, 24, 26] 1 2 A1 A2 3 4 5 A3 A4 6 7 8 9 10 CLK CEN CE ADV/LD WE BWX ADDRESS A5 tCHZ D(A1) Data Q(A2) D(A4) Q(A3) Q(A5) In-Out (DQ) WRITE D(A1) READ Q(A2) STALL READ Q(A3) WRITE D(A4) STALL DON’T CARE NOP READ Q(A5) DESELECT CONTINUE DESELECT UNDEFINED Note: 26. The IGNORE CLOCK EDGE or STALL cycle (Clock 3) illustrated CEN being used to create a pause.
PAGE 22
CY7C1354C CY7C1356C Switching Waveforms (continued) ZZ Mode Timing[27, 28] CLK t ZZ I t t ZZ ZZREC ZZI SUPPLY I t RZZI DDZZ ALL INPUTS (except ZZ) Outputs (Q) DESELECT or READ Only High-Z DON’T CARE 27. Device must be deselected when entering ZZ mode. See cycle description table for all possible signal conditions to deselect the device. 28. I/Os are in High-Z when exiting ZZ sleep mode. Document #: 38-05538 Rev.
PAGE 23
CY7C1354C CY7C1356C Ordering Information Not all of the speed, package and temperature ranges are available. Please contact your local sales representative or visit www.cypress.com for actual products offered. Speed (MHz) 166 Ordering Code CY7C1354C-166AXC Package Diagram Part and Package Type 51-85050 100-pin Thin Quad Flat Pack (14 x 20 x 1.4 mm) Lead-Free Operating Range Commercial CY7C1356C-166AXC CY7C1354C-166BGC 51-85115 119-ball Ball Grid Array (14 x 22 x 2.
PAGE 24
CY7C1354C CY7C1356C Ordering Information (continued) Not all of the speed, package and temperature ranges are available. Please contact your local sales representative or visit www.cypress.com for actual products offered. 250 CY7C1354C-250AXC 51-85050 100-pin Thin Quad Flat Pack (14 x 20 x 1.4 mm) Lead-Free Commercial CY7C1356C-250AXC CY7C1354C-250BGC 51-85115 119-ball Ball Grid Array (14 x 22 x 2.4 mm) CY7C1356C-250BGC CY7C1354C-250BGXC 51-85115 119-ball Ball Grid Array (14 x 22 x 2.
PAGE 25
CY7C1354C CY7C1356C Package Diagrams 100-Pin Thin Plastic Quad Flatpack (14 x 20 x 1.4 mm) (51-85050) 16.00±0.20 1.40±0.05 14.00±0.10 81 100 80 1 20.00±0.10 22.00±0.20 0.30±0.08 0.65 TYP. 30 12°±1° (8X) SEE DETAIL A 51 31 50 0.20 MAX. R 0.08 MIN. 0.20 MAX. 0.10 1.60 MAX. 0° MIN. SEATING PLANE STAND-OFF 0.05 MIN. 0.15 MAX. 0.25 NOTE: 1. JEDEC STD REF MS-026 GAUGE PLANE 0°-7° R 0.08 MIN. 0.20 MAX. 2.
PAGE 26
CY7C1354C CY7C1356C Package Diagrams (continued) 119-Ball BGA (14 x 22 x 2.4 mm) (51-85115) Ø0.05 M C Ø0.25 M C A B A1 CORNER Ø0.75±0.15(119X) Ø1.00(3X) REF. 1 2 3 4 5 6 7 7 6 5 4 3 2 1 A A B B C D 1.27 C D E E F F H 19.50 J K L 20.32 G H 22.00±0.20 G J K L M 10.16 M N P N P R R T T U U 1.27 0.70 REF. A 3.81 7.62 30° TYP. 14.00±0.20 0.15(4X) 0.15 C 2.40 MAX. B 0.90±0.05 0.25 C 12.00 51-85115-*B C Document #: 38-05538 Rev. *G 0.60±0.10 0.
PAGE 27
CY7C1354C CY7C1356C Package Diagrams (continued) 165 FBGA 13 x 15 x 1.40 MM BB165D/BW165D 165-Ball FBGA (13 x 15 x 1.4 mm) (51-85180) BOTTOM VIEW PIN 1 CORNER BOTTOM VIEW TOP VIEW PIN 1 CORNER TOP VIEW Ø0.05 M C Ø0.25 MØ0.05 CAB MC PIN 1 CORNER Ø0.25 M C A B Ø0.50 -0.06 (165X) PIN 1 CORNER 1 2 1 +0.14 4 2 5 3 6 4 7 5 8 6 9 7 10 11 8 9 11 10 11 10 9 11 8 10 7 9 6 8 5 7 Ø0.50 -0.06 (165X) 4 6 1 3 +0.14 2 5 4 3 2 1A B A C B C B D C D C E D F 1.
PAGE 28
CY7C1354C CY7C1356C Document History Page Document Title: CY7C1354C/CY7C1356C 9-Mbit (256K x 36/512K x 18) Pipelined SRAM with NoBL™ Architecture Document Number: 38-05538 REV. ECN No. Issue Date Orig.