Pipelined SRAM with NoBL Specifiation Sheet

CY7C1354C
CY7C1356C
Document #: 38-05538 Rev. *G Page 20 of 28
Switching Waveforms
Read/Write Timing
[23, 24, 25]
Notes:
23. For this waveform ZZ is tied low.
24. When CE
is LOW, CE
1
is LOW, CE
2
is HIGH and CE
3
is LOW. When CE is HIGH, CE
1
is HIGH or CE
2
is LOW or CE
3
is HIGH.
25. Order of the Burst sequence is determined by the status of the MODE (0 = Linear, 1 = Interleaved). Burst operations are optional.
WRITE
D(A1)
123456789
CLK
t
CYC
t
CL
t
CH
10
CE
t
CEH
t
CES
WE
CEN
t
CENH
t
CENS
BWX
ADV/LD
t
AH
t
AS
A
DDRESS
A1 A2
A3
A4
A5 A6 A7
t
DH
t
DS
Data
n-
Out (DQ)
t
CLZ
D(A1) D(A2) D(A5)Q(A4)Q(A3)
D(A2+1)
t
DOH
t
CHZ
t
CO
WRITE
D(A2)
BURST
WRITE
D(A2+1)
READ
Q(A3)
READ
Q(A4)
BURST
READ
Q(A4+1)
WRITE
D(A5)
READ
Q(A6)
WRITE
D(A7)
DESELE
CT
OE
t
OEV
t
OELZ
t
OEHZ
t
DOH
DON’T CARE UNDEFINED
Q(A
6)
Q(A4+1)
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