Computer Hardware Specification Sheet

ManualsBrandsCypress ManualsComputer HardwarePerform CY7C1382D

CY7C1380D, CY7C1382D

CY7C1380F, CY7C1382F

18-Mbit (512K x 36/1M x 18)

Pipelined SRAM

Cypress Semiconductor Corporation • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600

Document #: 38-05543 Rev. *F Revised January 12, 2009

Features

■ Supports bus operation up to 250 MHz

■ Available speed grades are 250, 200, and 167 MHz

■ Registered inputs and outputs for pipelined operation

■ 3.3V core power supply

■ 2.5V or 3.3V I/O power supply

■ Fast clock-to-output times

❐ 2.6 ns (for 250 MHz device)

■ Provides high performance 3-1-1-1 access rate

■ User selectable burst counter supporting Intel

Pentium

inter-

leaved or linear burst sequences

■ Separate processor and controller address strobes

■ Synchronous self-timed write

■ Asynchronous output enable

■ Single cycle chip deselect

■ CY7C1380D/CY7C1382D is available in JEDEC-standard

Pb-free 100-pin TQFP, Pb-free and non Pb-free 165-ball FBGA

package; CY7C1380F/CY7C1382F is available in

JEDEC-standard Pb-free 100-pin TQFP, Pb-free and non

Pb-free 119-ball BGA and 165-ball FBGA package

■ IEEE 1149.1 JTAG-Compatible Boundary Scan

■ ZZ sleep mode option

Functional Description

The CY7C1380D/CY7C1382D/CY7C1380F/CY7C1382F

[1]

SRAM integrates 524,288 x 36 and 1,048,576 x 18 SRAM cells

with advanced synchronous peripheral circuitry and a two-bit

counter for internal burst operation. All synchronous inputs are

gated by registers controlled by a positive edge triggered clock

input (CLK). The synchronous inputs include all addresses, all

data inputs, address-pipelining chip enable (CE

depth-expansion chip enables (CE

and CE

[2]

), burst control

inputs (ADSC, ADSP, and ADV), write enables (BW

, and BWE),

and global write (GW). Asynchronous inputs include the output

enable (OE

) and the ZZ pin.

Addresses and chip enables are registered at rising edge of

clock when address strobe processor (ADSP

) or address strobe

controller (ADSC) are active. Subsequent burst addresses can

be internally generated as they are controlled by the advance pin

(ADV

Address, data inputs, and write controls are registered on-chip

to initiate a self-timed write cycle.This part supports byte write

operations (see Ta ble 1 on page 6 and “Truth Table” on page 10

for further details). Write cycles can be one to two or four bytes

wide as controlled by the byte write control inputs. GW

when

active LOW causes all bytes to be written.

The CY7C1380D/CY7C1382D/CY7C1380F/CY7C1382F

operates from a +3.3V core power supply while all outputs

operate with a +2.5 or +3.3V power supply. All inputs and outputs

are JEDEC-standard and JESD8-5-compatible.

Selection Guide

Description 250 MHz 200 MHz 167 MHz Unit

Maximum Access Time 2.6 3.0 3.4 ns

Maximum Operating Current 350 300 275 mA

Maximum CMOS Standby Current 70 70 70 mA

Notes

1. For best practices or recommendations, please refer to the Cypress application note AN1064, SRAM System Design Guidelines on www.cypress.com.

2. CE

are for TQFP and 165 FBGA packages only. 119 BGA is offered only in 1 chip enable.

[+] Feedback

Summary of content (34 pages)

PAGE 1
CY7C1380D, CY7C1382D CY7C1380F, CY7C1382F 18-Mbit (512K x 36/1M x 18) Pipelined SRAM Features Functional Description ■ Supports bus operation up to 250 MHz ■ Available speed grades are 250, 200, and 167 MHz ■ Registered inputs and outputs for pipelined operation ■ 3.3V core power supply ■ 2.5V or 3.3V I/O power supply ■ Fast clock-to-output times ❐ 2.
PAGE 2
CY7C1380D, CY7C1382D CY7C1380F, CY7C1382F Logic Block Diagram – CY7C1380D/CY7C1380F [3] (512K x 36) A0, A1, A ADDRESS REGISTER 2 A [1:0] MODE ADV CLK Q1 BURST COUNTER CLR AND LOGIC ADSC Q0 ADSP BW D DQ D , DQP D BYTE WRITE REGISTER DQ D ,DQP D BYTE WRITE DRIVER BW C DQ C , DQP C BYTE WRITE REGISTER DQ C , DQP C BYTE WRITE DRIVER DQ B , DQP B BYTE WRITE REGISTER DQ B , DQP B BYTE WRITE DRIVER BW B BW A BWE ZZ ENABLE REGISTER SENSE AMPS OUTPUT REGISTERS OUTPUT BUFFERS E DQs DQP A DQP
PAGE 3
CY7C1380D, CY7C1382D CY7C1380F, CY7C1382F Pin Configurations 100-Pin TQFP Pinout (3-Chip Enable) Figure 1. CY7C1380D, CY7C1380F(512K X 36) Document #: 38-05543 Rev. *F Figure 2.
PAGE 4
CY7C1380D, CY7C1382D CY7C1380F, CY7C1382F 119-Ball BGA Pinout 1 Figure 3.
PAGE 5
CY7C1380D, CY7C1382D CY7C1380F, CY7C1382F 165-Ball FBGA Pinout (3-Chip Enable) Figure 5.
PAGE 6
CY7C1380D, CY7C1382D CY7C1380F, CY7C1382F Table 1. Pin Definitions Name I/O Description A0, A1, A InputAddress inputs used to select one of the address locations. Sampled at the rising edge of Synchronous the CLK if ADSP or ADSC is active LOW, and CE1, CE2, and CE3 [2]are sampled active. A1: A0 are fed to the two-bit counter.. BWA, BWB BWC, BWD InputByte write select inputs, active LOW. Qualified with BWE to conduct byte writes to the SRAM. Synchronous Sampled on the rising edge of CLK.
PAGE 7
CY7C1380D, CY7C1382D CY7C1380F, CY7C1382F Table 1. Pin Definitions (continued) MODE Input-Static Selects burst order. When tied to GND selects linear burst sequence. When tied to VDD or left floating selects interleaved burst sequence. This is a strap pin and must remain static during device operation. Mode pin has an internal pull up. TDO JTAG serial Serial data-out to the JTAG circuit. Delivers data on the negative edge of TCK.
PAGE 8
CY7C1380D, CY7C1382D CY7C1380F, CY7C1382F Functional Overview Single Write Accesses Initiated by ADSP All synchronous inputs pass through input registers controlled by the rising edge of the clock. All data outputs pass through output registers controlled by the rising edge of the clock. Maximum access delay from the clock rise (tCO) is 2.6 ns (250 MHz device). The CY7C1380D/CY7C1382D/CY7C1380F/CY7C1382F supports secondary cache in systems using a linear or interleaved burst sequence.
PAGE 9
CY7C1380D, CY7C1382D CY7C1380F, CY7C1382F Burst Sequences The CY7C1380D/CY7C1382D/CY7C1380F/CY7C1382F provides a two-bit wraparound counter, fed by A1: A0, that implements an interleaved or a linear burst sequence. The interleaved burst sequence is designed specifically to support Intel Pentium applications. The linear burst sequence is designed to support processors that follow a linear burst sequence. The burst sequence is user selectable through the MODE input.
PAGE 10
CY7C1380D, CY7C1382D CY7C1380F, CY7C1382F Truth Table The Truth Table for this data sheet follows.[4, 5, 6, 7, 8] Operation Add.
PAGE 11
CY7C1380D, CY7C1382D CY7C1380F, CY7C1382F Truth Table for Read/Write [4, 9] Function (CY7C1380D/CY7C1380F) GW BWE BWD BWC BWB BWA Read H H X X X X Read H L H H H H Write Byte A – (DQA and DQPA) Write Byte B – (DQB and DQPB) H L H H H L H L H H L H Write Bytes B, A H L H H L L Write Byte C – (DQC and DQPC) H L H L H H Write Bytes C, A H L H L H L Write Bytes C, B H L H L L H Write Bytes C, B, A H L H L L L Write Byte D – (DQD and DQPD) H
PAGE 12
CY7C1380D, CY7C1382D CY7C1380F, CY7C1382F IEEE 1149.1 Serial Boundary Scan (JTAG) The CY7C1380D/CY7C1382D incorporates a serial boundary scan test access port (TAP).This part is fully compliant with 1149.1. The TAP operates using JEDEC-standard 3.3V or 2.5V I/O logic levels. The CY7C1380D/CY7C1382D contains a TAP controller, instruction register, boundary scan register, bypass register, and ID register. Disabling the JTAG Feature It is possible to operate the SRAM without using the JTAG feature.
PAGE 13
CY7C1380D, CY7C1382D CY7C1380F, CY7C1382F When the TAP controller is in the Capture-IR state, the two least significant bits are loaded with a binary ‘01’ pattern to enable fault isolation of the board-level serial test data path. Bypass Register To save time when serially shifting data through registers, it is sometimes advantageous to skip certain chips. The bypass register is a single-bit register that can be placed between the TDI and TDO balls.
PAGE 14
CY7C1380D, CY7C1382D CY7C1380F, CY7C1382F when the EXTEST is entered as the current instruction. When HIGH, it enables the output buffers to drive the output bus. When LOW, this bit places the output bus into a High-Z condition. output Q-bus pins. Note that this bit is preset HIGH to enable the output when the device is powered up, and also when the TAP controller is in the Test-Logic-Reset state.
PAGE 15
CY7C1380D, CY7C1382D CY7C1380F, CY7C1382F 3.3V TAP AC Test Conditions 2.5V TAP AC Test Conditions Input pulse levels.................................................VSS to 3.3V Input pulse levels................................................. VSS to 2.5V Input rise and fall times....................................................1 ns Input rise and fall time .....................................................1 ns Input timing reference levels................... ........................1.
PAGE 16
CY7C1380D, CY7C1382D CY7C1380F, CY7C1382F Identification Register Definitions CY7C1380D/CY7C1380F CY7C1382D/CY7C1382F (512K x 36) (1 Mbit x 18) Instruction Field Description Revision Number (31:29) 000 000 Device Depth (28:24) [13] 01011 01011 Device Width (23:18) 119-BGA 101000 101000 Defines the memory type and architecture. Device Width (23:18) 165-FBGA 000000 000000 Defines the memory type and architecture.
PAGE 17
CY7C1380D, CY7C1382D CY7C1380F, CY7C1382F 119-Ball BGA Boundary Scan Order [14, 15] Bit # Ball ID Bit # Ball ID Bit # Ball ID 1 H4 T4 23 2 24 3 T5 25 4 T6 26 5 R5 27 G6 49 6 L5 28 E6 50 7 R6 29 D6 51 8 U6 30 C7 52 9 R7 31 B7 53 10 T7 32 C6 54 Bit # Ball ID F6 45 G4 67 L1 E7 46 A4 68 M2 D7 47 G3 69 N1 H7 48 C3 70 P1 B2 71 K1 B3 72 L2 A3 73 C2 74 N2 P2 A2 75 R3 B1 76 T1 11 P6 33 A6 55 C1 77 R1 12 N7 34 C5 56 D2
PAGE 18
CY7C1380D, CY7C1382D CY7C1380F, CY7C1382F 165-Ball BGA Boundary Scan Order [14, 16] Bit # Ball ID Bit # Ball ID 1 2 3 N10 4 P11 Bit # Ball ID N6 31 N7 32 D10 61 G1 C11 62 D2 33 A11 63 E2 34 B11 64 F2 5 P8 35 A10 65 G2 6 R8 36 B10 66 H1 7 R9 37 A9 67 H3 8 P9 38 B9 68 J1 9 P10 39 C10 69 K1 10 R10 40 A8 70 L1 11 R11 41 B8 71 M1 12 H11 42 A7 72 J2 13 N11 43 B7 73 K2 14 M11 44 B6 74 L2 15 L11 45 A6 75 M2 16 K11 46 B
PAGE 19
CY7C1380D, CY7C1382D CY7C1380F, CY7C1382F Maximum Ratings DC Input Voltage ................................... –0.5V to VDD + 0.5V Current into Outputs (LOW)......................................... 20 mA Exceeding the maximum ratings may impair the useful life of the device. For user guidelines, not tested. Static Discharge Voltage........................................... >2001V (per MIL-STD-883, Method 3015) Storage Temperature ................................. –65°C to +150°C Latch-up Current....
PAGE 20
CY7C1380D, CY7C1382D CY7C1380F, CY7C1382F Capacitance [19] Parameter Description CIN Input Capacitance CCLK Clock Input Capacitance CIO Input/Output Capacitance 100 TQFP Package 119 BGA Package 165 FBGA Package Unit 5 8 9 pF 5 8 9 pF 5 8 9 pF Test Conditions 100 TQFP Package 119 BGA Package 165 FBGA Package Unit Test conditions follow standard test methods and procedures for measuring thermal impedance, in accordance with EIA/JESD51. 28.66 23.8 20.7 °C/W 4.08 6.2 4.
PAGE 21
CY7C1380D, CY7C1382D CY7C1380F, CY7C1382F Figure 9. AC Test Loads and Waveforms 3.3V I/O Test Load R = 317Ω 3.3V OUTPUT OUTPUT RL = 50Ω Z0 = 50Ω GND 5 pF R = 351Ω VT = 1.5V INCLUDING JIG AND SCOPE (a) 2.5V I/O Test Load OUTPUT RL = 50Ω Z0 = 50Ω VT = 1.25V (a) 10% (c) ALL INPUT PULSES VDDQ INCLUDING JIG AND SCOPE ≤ 1 ns (b) GND 5 pF 90% 10% 90% ≤ 1 ns R = 1667Ω 2.5V OUTPUT ALL INPUT PULSES VDDQ R = 1538Ω (b) 10% 90% 10% 90% ≤ 1 ns ≤ 1 ns (c) Note 19.
PAGE 22
CY7C1380D, CY7C1382D CY7C1380F, CY7C1382F Switching Characteristics Over the Operating Range [20, 21] Description Parameter tPOWER VDD(Typical) to the first Access [22] 250 MHz Min Max 200 MHz Min Max 167 MHz Min Max Unit 1 1 1 ms Clock tCYC Clock Cycle Time 4.0 5 6 ns tCH Clock HIGH 1.7 2.0 2.2 ns tCL Clock LOW 1.7 2.0 2.2 ns Output Times tCO Data Output Valid After CLK Rise tDOH Data Output Hold After CLK Rise 1.0 1.3 1.3 ns tCLZ Clock to Low-Z [23, 24, 25] 1.
PAGE 23
CY7C1380D, CY7C1382D CY7C1380F, CY7C1382F Switching Waveforms Figure 10. Read Cycle Timing [26] t CYC CLK t t ADS CH t CL t ADH ADSP t ADS tADH ADSC t AS tAH A1 ADDRESS A2 t WES A3 Burst continued with new base address tWEH GW, BWE, BWx t CES Deselect cycle tCEH CE t ADVS tADVH ADV ADV suspends burst.
PAGE 24
CY7C1380D, CY7C1382D CY7C1380F, CY7C1382F Switching Waveforms (continued) Figure 11.
PAGE 25
CY7C1380D, CY7C1382D CY7C1380F, CY7C1382F Switching Waveforms (continued) Figure 12. Read/Write Cycle Timing [26, 28, 29] tCYC CLK tCL tCH t ADS tADH t AS tAH ADSP ADSC ADDRESS A1 A2 A3 A4 A5 A6 t WES tWEH BWE, BW X t CES tCEH CE ADV OE t DS tCO tDH t OELZ Data In (D) High-Z tCLZ Data Out (Q) High-Z Q(A1) Back-to-Back READs tOEHZ D(A5) D(A3) Q(A2) Q(A4) Single WRITE Q(A4+1) Q(A4+2) BURST READ DON’T CARE D(A6) Q(A4+3) Back-to-Back WRITEs UNDEFINED Notes 28.
PAGE 26
CY7C1380D, CY7C1382D CY7C1380F, CY7C1382F Switching Waveforms (continued) Figure 13. ZZ Mode Timing [30, 31] CLK t ZZ I t t ZZ ZZREC ZZI SUPPLY I t RZZI DDZZ ALL INPUTS (except ZZ) Outputs (Q) DESELECT or READ Only High-Z DON’T CARE Notes 30. Device must be deselected when entering ZZ mode. See “Truth Table” on page 10 for all possible signal conditions to deselect the device. 31. DQs are in high-Z when exiting ZZ sleep mode. Document #: 38-05543 Rev.
PAGE 27
CY7C1380D, CY7C1382D CY7C1380F, CY7C1382F Ordering Information The following table lists all speed, package and temperature range options. Please note that some options listed below may not be available for order entry. To verify the availability of a specific option, visit the Cypress website at www.cypress.com and refer to the product summary page at http://www.cypress.com/products, or contact your local sales representative for the status of availability of parts.
PAGE 28
CY7C1380D, CY7C1382D CY7C1380F, CY7C1382F Speed (MHz) 200 Ordering Code CY7C1380D-200AXC Package Diagram Part and Package Type 51-85050 100-pin Thin Quad Flat Pack (14 x 20 x 1.4 mm) Pb-Free Operating Range Commercial CY7C1382D-200AXC CY7C1380F-200AXC CY7C1382F-200AXC CY7C1380F-200BGC 51-85115 119-ball Ball Grid Array (14 x 22 x 2.4 mm) CY7C1382F-200BGC CY7C1380F-200BGXC 51-85115 119-ball Ball Grid Array (14 x 22 x 2.
PAGE 29
CY7C1380D, CY7C1382D CY7C1380F, CY7C1382F Speed (MHz) 167 Ordering Code CY7C1380D-167AXC Package Diagram Part and Package Type 51-85050 100-pin Thin Quad Flat Pack (14 x 20 x 1.4 mm) Pb-Free Operating Range Commercial CY7C1382D-167AXC CY7C1380F-167AXC CY7C1382F-167AXC CY7C1380F-167BGC 51-85115 119-ball Ball Grid Array (14 x 22 x 2.4 mm) CY7C1382F-167BGC CY7C1380F-167BGXC 51-85115 119-ball Ball Grid Array (14 x 22 x 2.
PAGE 30
CY7C1380D, CY7C1382D CY7C1380F, CY7C1382F Package Diagrams Figure 14. 100-Pin Thin Plastic Quad Flat Pack (14 x 20 x 1.4 mm) (51-85050) 16.00±0.20 1.40±0.05 14.00±0.10 100 81 80 1 20.00±0.10 22.00±0.20 0.30±0.08 0.65 TYP. 30 12°±1° (8X) SEE DETAIL A 51 31 50 0.20 MAX. 0.10 1.60 MAX. R 0.08 MIN. 0.20 MAX. 0° MIN. SEATING PLANE STAND-OFF 0.05 MIN. 0.15 MAX. 0.25 NOTE: 1. JEDEC STD REF MS-026 GAUGE PLANE 0°-7° R 0.08 MIN. 0.20 MAX. 2.
PAGE 31
CY7C1380D, CY7C1382D CY7C1380F, CY7C1382F Package Diagrams (continued) Figure 15. 119-Ball BGA (14 x 22 x 2.4 mm) (51-85115) 51-85115-*B Document #: 38-05543 Rev.
PAGE 32
CY7C1380D, CY7C1382D CY7C1380F, CY7C1382F Package Diagrams (continued) Figure 16. 165-Ball FBGA (13 x 15 x 1.4 mm) (51-85180) 165 FBGA 13 x 15 x 1.40 MM BB165D/BW165D BOTTOM VIEW PIN 1 CORNER BOTTOM VIEW TOP VIEW PIN 1 CORNER TOP VIEW Ø0.05 M C Ø0.25 MØ0.05 CAB MC PIN 1 CORNER Ø0.25 M C A B Ø0.50 -0.06 (165X) PIN 1 CORNER 1 2 1 +0.14 4 2 5 3 6 4 7 5 8 6 9 7 10 11 8 9 11 10 11 10 9 11 8 10 7 9 6 8 5 7 Ø0.50 -0.06 (165X) 4 6 1 3 +0.
PAGE 33
CY7C1380D, CY7C1382D CY7C1380F, CY7C1382F Document History Page Document Title: CY7C1380D/CY7C1382D/CY7C1380F/CY7C1382F, 18-Mbit (512K x 36/1M x 18) Pipelined SRAM Document Number: 38-05543 REV. ECN NO. Submission Date Orig. of Change Description of Change ** 254515 See ECN RKF New data sheet *A 288531 See ECN SYT Edited description under “IEEE 1149.1 Serial Boundary Scan (JTAG)” for non-compliance with 1149.
PAGE 34
CY7C1380D, CY7C1382D CY7C1380F, CY7C1382F Sales, Solutions, and Legal Information Worldwide Sales and Design Support Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office closest to you, visit us at cypress.com/sales. Products PSoC Clocks & Buffers PSoC Solutions psoc.cypress.com clocks.cypress.com General Low Power/Low Voltage psoc.cypress.com/solutions psoc.cypress.com/low-power Wireless wireless.cypress.