SRAM 4-Word Burst Architecture Specification Sheet

ManualsBrandsCypress ManualsComputer HardwarePerform CY7C1513KV18

72-Mbit QDR™-II SRAM 4-Word

Burst Architecture

CY7C1511KV18, CY7C1526KV18

CY7C1513KV18, CY7C1515KV18

Cypress Semiconductor Corporation • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600

Document Number: 001-00435 Rev. *E Revised March 30, 2009

Features

■ Separate Independent Read and Write Data Ports

❐ Supports concurrent transactions

■ 333 MHz Clock for High Bandwidth

■ 4-word Burst for Reducing Address Bus Frequency

■ Double Data Rate (DDR) Interfaces on both Read and Write

Ports (data transferred at 666 MHz) at 333 MHz

■ Two Input Clocks (K and K) for precise DDR Timing

❐ SRAM uses rising edges only

■ Two Input Clocks for Output Data (C and C) to minimize Clock

Skew and Flight Time mismatches

■ Echo Clocks (CQ and CQ) simplify Data Capture in High Speed

Systems

■ Single Multiplexed Address Input Bus latches Address Inputs

for Read and Write Ports

■ Separate Port Selects for Depth Expansion

■ Synchronous Internally Self-timed Writes

■ QDR™-II operates with 1.5 Cycle Read Latency when DOFF

is asserted HIGH

■ Operates similar to QDR-I Device with 1 Cycle Read Latency

when DOFF

is asserted LOW

■ Available in x8, x9, x18, and x36 Configurations

■ Full Data Coherency, providing Most Current Data

■ Core V

= 1.8V (±0.1V); IO V

DDQ

= 1.4V to V

❐ Supports both 1.5V and 1.8V IO supply

■ Available in 165-ball FBGA Package (13 x 15 x 1.4 mm)

■ Offered in both Pb-free and non Pb-free Packages

■ Variable Drive HSTL Output Buffers

■ JTAG 1149.1 Compatible Test Access Port

■ Phase Locked Loop (PLL) for Accurate Data Placement

Configurations

CY7C1511KV18 – 8M x 8

CY7C1526KV18 – 8M x 9

CY7C1513KV18 – 4M x 18

CY7C1515KV18 – 2M x 36

Functional Description

The CY7C1511KV18, CY7C1526KV18, CY7C1513KV18, and

CY7C1515KV18 are 1.8V Synchronous Pipelined SRAMs,

equipped with QDR-II architecture. QDR-II architecture consists

of two separate ports: the read port and the write port to access

the memory array. The read port has dedicated data outputs to

support read operations and the write port has dedicated data

inputs to support write operations. QDR-II architecture has

separate data inputs and data outputs to completely eliminate

the need to “turnaround” the data bus that exists with common

IO devices. Each port can be accessed through a common

address bus. Addresses for read and write addresses are

latched on alternate rising edges of the input (K) clock. Accesses

to the QDR-II read and write ports are independent of one

another. To maximize data throughput, both read and write ports

are equipped with DDR interfaces. Each address location is

associated with four 8-bit words (CY7C1511KV18), 9-bit words

(CY7C1526KV18), 18-bit words (CY7C1513KV18), or 36-bit

words (CY7C1515KV18) that burst sequentially into or out of the

device. Because data can be transferred into and out of the

device on every rising edge of both input clocks (K and K

and C

), memory bandwidth is maximized while simplifying

system design by eliminating bus “turnarounds”.

Depth expansion is accomplished with port selects, which

enables each port to operate independently.

All synchronous inputs pass through input registers controlled by

the K or K

input clocks. All data outputs pass through output

registers controlled by the C or C

(or K or K in a single clock

domain) input clocks. Writes are conducted with on-chip

synchronous self-timed write circuitry.

Table 1. Selection Guide

Description 333 MHz 300 MHz 250 MHz 200 MHz 167 MHz Unit

Maximum Operating Frequency 333 300 250 200 167 MHz

Maximum Operating Current x8 600 560 490 430 380 mA

x9 600 560 490 430 380

x18 620 570 500 440 390

x36 850 790 680 580 510

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Summary of content (31 pages)

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CY7C1511KV18, CY7C1526KV18 CY7C1513KV18, CY7C1515KV18 72-Mbit QDR™-II SRAM 4-Word Burst Architecture Features Configurations ■ Separate Independent Read and Write Data Ports ❐ Supports concurrent transactions CY7C1511KV18 – 8M x 8 ■ 333 MHz Clock for High Bandwidth CY7C1513KV18 – 4M x 18 ■ 4-word Burst for Reducing Address Bus Frequency CY7C1515KV18 – 2M x 36 ■ Double Data Rate (DDR) Interfaces on both Read and Write Ports (data transferred at 666 MHz) at 333 MHz Functional Description ■ Two
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CY7C1511KV18, CY7C1526KV18 CY7C1513KV18, CY7C1515KV18 Logic Block Diagram (CY7C1511KV18) DOFF Write Reg Address Register Read Add. Decode 2M x 8 Array K CLK Gen. Write Reg 2M x 8 Array K Write Reg 2M x 8 Array Address Register Write Reg 2M x 8 Array A(20:0) 21 8 Write Add. Decode D[7:0] 21 A(20:0) RPS Control Logic C Read Data Reg. C CQ 32 VREF WPS NWS[1:0] 16 Control Logic Reg. 16 Reg. CQ Reg.
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CY7C1511KV18, CY7C1526KV18 CY7C1513KV18, CY7C1515KV18 Logic Block Diagram (CY7C1513KV18) DOFF Address Register Read Add. Decode Write Reg 1M x 18 Array K CLK Gen. Write Reg 1M x 18 Array K Write Reg 1M x 18 Array Address Register Write Reg 1M x 18 Array A(19:0) 20 18 Write Add. Decode D[17:0] Control Logic 20 A(19:0) RPS C Read Data Reg. C CQ 72 VREF WPS BWS[1:0] 36 Control Logic Reg. 36 Reg. CQ Reg.
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CY7C1511KV18, CY7C1526KV18 CY7C1513KV18, CY7C1515KV18 Pin Configuration The pin configurations for CY7C1511KV18, CY7C1526KV18, CY7C1513KV18, and CY7C1515KV18 follow. [1] 165-Ball FBGA (13 x 15 x 1.
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CY7C1511KV18, CY7C1526KV18 CY7C1513KV18, CY7C1515KV18 Pin Configuration (continued) The pin configurations for CY7C1511KV18, CY7C1526KV18, CY7C1513KV18, and CY7C1515KV18 follow. [1] 165-Ball FBGA (13 x 15 x 1.
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CY7C1511KV18, CY7C1526KV18 CY7C1513KV18, CY7C1515KV18 Pin Definitions Pin Name I/O Pin Description D[x:0] InputData Input Signals. Sampled on the rising edge of K and K clocks when valid write operations are active. Synchronous CY7C1511KV18 − D[7:0] CY7C1526KV18 − D[8:0] CY7C1513KV18 − D[17:0] CY7C1515KV18 − D[35:0] WPS InputWrite Port Select − Active LOW. Sampled on the rising edge of the K clock. When asserted active, a Synchronous write operation is initiated. Deasserting deselects the write port.
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CY7C1511KV18, CY7C1526KV18 CY7C1513KV18, CY7C1515KV18 Pin Definitions Pin Name (continued) I/O Pin Description CQ Echo Clock CQ Referenced with Respect to C. This is a free running clock and is synchronized to the input clock for output data (C) of the QDR-II. In the single clock mode, CQ is generated with respect to K. The timings for the echo clocks are shown in the Switching Characteristics on page 24. CQ Echo Clock CQ Referenced with Respect to C.
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CY7C1511KV18, CY7C1526KV18 CY7C1513KV18, CY7C1515KV18 Functional Overview The CY7C1511KV18, CY7C1526KV18, CY7C1513KV18, CY7C1515KV18 are synchronous pipelined Burst SRAMs with a read port and a write port. The read port is dedicated to read operations and the write port is dedicated to write operations. Data flows into the SRAM through the write port and flows out through the read port. These devices multiplex the address inputs to minimize the number of address pins required.
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CY7C1511KV18, CY7C1526KV18 CY7C1513KV18, CY7C1515KV18 Single Clock Mode Programmable Impedance The CY7C1511KV18 is used with a single clock that controls both the input and output registers. In this mode the device recognizes only a single pair of input clocks (K and K) that control both the input and output registers. This operation is identical to the operation if the device had zero skew between the K/K and C/C clocks. All timing parameters remain the same in this mode.
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CY7C1511KV18, CY7C1526KV18 CY7C1513KV18, CY7C1515KV18 Application Example Figure 1 shows four QDR-II used in an application. Figure 1.
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CY7C1511KV18, CY7C1526KV18 CY7C1513KV18, CY7C1515KV18 Write Cycle Descriptions The write cycle description table for CY7C1511KV18 and CY7C1513KV18 follows. [2, 10] BWS0/ BWS1/ K K L L–H – L L – L H L–H L H – H L L–H H L – H H L–H H H – NWS0 NWS1 L Comments During the data portion of a write sequence: CY7C1511KV18 − both nibbles (D[7:0]) are written into the device. CY7C1513KV18 − both bytes (D[17:0]) are written into the device.
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CY7C1511KV18, CY7C1526KV18 CY7C1513KV18, CY7C1515KV18 Write Cycle Descriptions The write cycle description table for CY7C1515KV18 follows. [2, 10] BWS0 BWS1 BWS2 BWS3 K K Comments L L L L L–H – During the data portion of a write sequence, all four bytes (D[35:0]) are written into the device.
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CY7C1511KV18, CY7C1526KV18 CY7C1513KV18, CY7C1515KV18 IEEE 1149.1 Serial Boundary Scan (JTAG) These SRAMs incorporate a serial boundary scan Test Access Port (TAP) in the FBGA package. This part is fully compliant with IEEE Standard #1149.1-2001. The TAP operates using JEDEC standard 1.8V IO logic levels. Disabling the JTAG Feature It is possible to operate the SRAM without using the JTAG feature. To disable the TAP controller, TCK must be tied LOW (VSS) to prevent clocking of the device.
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CY7C1511KV18, CY7C1526KV18 CY7C1513KV18, CY7C1515KV18 IDCODE The IDCODE instruction loads a vendor-specific, 32-bit code into the instruction register. It also places the instruction register between the TDI and TDO pins and shifts the IDCODE out of the device when the TAP controller enters the Shift-DR state. The IDCODE instruction is loaded into the instruction register at power up or whenever the TAP controller is supplied a Test-Logic-Reset state.
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CY7C1511KV18, CY7C1526KV18 CY7C1513KV18, CY7C1515KV18 TAP Controller State Diagram The state diagram for the TAP controller follows. [11] 1 TEST-LOGIC RESET 0 0 TEST-LOGIC/ IDLE 1 SELECT DR-SCAN 1 1 SELECT IR-SCAN 0 0 1 1 CAPTURE-DR CAPTURE-IR 0 0 SHIFT-DR 0 SHIFT-IR 1 1 EXIT1-DR 1 EXIT1-IR 0 0 PAUSE-IR 1 0 1 EXIT2-DR 0 EXIT2-IR 1 1 UPDATE-IR UPDATE-DR 1 1 0 PAUSE-DR 0 0 0 1 0 Note 11. The 0/1 next to each state represents the value at TMS at the rising edge of TCK.
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CY7C1511KV18, CY7C1526KV18 CY7C1513KV18, CY7C1515KV18 TAP Controller Block Diagram 0 Bypass Register 2 Selection Circuitry TDI 1 0 Selection Circuitry Instruction Register 31 30 29 . . 2 1 0 1 0 TDO Identification Register 108 . . . . 2 Boundary Scan Register TCK TAP Controller TMS TAP Electrical Characteristics Over the Operating Range [12, 13, 14] Parameter Description Test Conditions Min Max Unit VOH1 Output HIGH Voltage IOH = −2.0 mA 1.
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CY7C1511KV18, CY7C1526KV18 CY7C1513KV18, CY7C1515KV18 TAP AC Switching Characteristics Over the Operating Range [15, 16] Parameter Description Min Max Unit 20 MHz tTCYC TCK Clock Cycle Time tTF TCK Clock Frequency tTH TCK Clock HIGH 20 ns tTL TCK Clock LOW 20 ns tTMSS TMS Setup to TCK Clock Rise 5 ns tTDIS TDI Setup to TCK Clock Rise 5 ns tCS Capture Setup to TCK Rise 5 ns tTMSH TMS Hold after TCK Clock Rise 5 ns tTDIH TDI Hold after Clock Rise 5 ns tCH Capture Hold a
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CY7C1511KV18, CY7C1526KV18 CY7C1513KV18, CY7C1515KV18 Identification Register Definitions Instruction Field Value CY7C1511KV18 CY7C1526KV18 CY7C1513KV18 CY7C1515KV18 000 000 000 000 Revision Number (31:29) Description Version number. Cypress Device ID 11010011011000100 11010011011001100 11010011011010100 11010011011100100 Defines the type of (28:12) SRAM.
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CY7C1511KV18, CY7C1526KV18 CY7C1513KV18, CY7C1515KV18 Boundary Scan Order Bit # Bump ID Bit # Bump ID Bit # Bump ID Bit # Bump ID 0 6R 28 10G 56 6A 84 1J 1 6P 29 9G 57 5B 85 2J 2 6N 30 11F 58 5A 86 3K 3 7P 31 11G 59 4A 87 3J 4 7N 32 9F 60 5C 88 2K 5 7R 33 10F 61 4B 89 1K 6 8R 34 11E 62 3A 90 2L 7 8P 35 10E 63 2A 91 3L 8 9R 36 10D 64 1A 92 1M 9 11P 37 9E 65 2B 93 1L 10 10P 38 10C 66 3B 94 3N 3M 11 10N 39 11D 6
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CY7C1511KV18, CY7C1526KV18 CY7C1513KV18, CY7C1515KV18 Power Up Sequence in QDR-II SRAM PLL Constraints QDR-II SRAMs must be powered up and initialized in a predefined manner to prevent undefined operations. ■ PLL uses K clock as its synchronizing input. The input must have low phase jitter, which is specified as tKC Var. ■ The PLL functions at frequencies down to 120 MHz.
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CY7C1511KV18, CY7C1526KV18 CY7C1513KV18, CY7C1515KV18 Maximum Ratings Current into Outputs (LOW) ........................................ 20 mA Exceeding maximum ratings may impair the useful life of the device. These user guidelines are not tested. Storage Temperature ................................. –65°C to +150°C Static Discharge Voltage (MIL-STD-883, M. 3015).. > 2001V Latch up Current....................................................
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CY7C1511KV18, CY7C1526KV18 CY7C1513KV18, CY7C1515KV18 Electrical Characteristics (continued) DC Electrical Characteristics Over the Operating Range [14] Parameter IDD [21] Description VDD Operating Supply Test Conditions VDD = Max, IOUT = 0 mA, f = fMAX = 1/tCYC 200 MHz 167 MHz ISB1 Automatic Power Down Current Max VDD, Both Ports Deselected, VIN ≥ VIH or VIN ≤ VIL f = fMAX = 1/tCYC, Inputs Static 333 MHz 300 MHz 250 MHz 200 MHz 167 MHz Min Typ Max Unit (x8) 430 mA (x9) 430 (x18) 4
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CY7C1511KV18, CY7C1526KV18 CY7C1513KV18, CY7C1515KV18 Capacitance Tested initially and after any design or process change that may affect these parameters. Parameter Description CIN Input Capacitance CO Output Capacitance Test Conditions TA = 25°C, f = 1 MHz, VDD = 1.8V, VDDQ = 1.5V Max Unit 2 pF 3 pF 165 FBGA Package Unit 13.7 °C/W 3.73 °C/W Thermal Resistance Tested initially and after any design or process change that may affect these parameters.
PAGE 24
CY7C1511KV18, CY7C1526KV18 CY7C1513KV18, CY7C1515KV18 Switching Characteristics Over the Operating Range [22, 23] Cypress Consortium Parameter Parameter Description VDD(Typical) to the First Access [24] tPOWER 333 MHz 300 MHz 250 MHz 200 MHz 167 MHz Min Max Min Max Min Max Min Max Min Max 1 1 1 1 1 Unit ms tCYC tKHKH K Clock and C Clock Cycle Time 3.0 8.4 3.3 8.4 4.0 8.4 5.0 8.4 6.0 8.4 ns tKH tKHKL Input Clock (K/K; C/C) HIGH 1.20 – 1.32 – 1.6 – 2.0 – 2.
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CY7C1511KV18, CY7C1526KV18 CY7C1513KV18, CY7C1515KV18 Switching Characteristics Over the Operating Range [22, 23] Cypress Consortium Parameter Parameter (continued) Description 333 MHz 300 MHz 250 MHz 200 MHz 167 MHz Min Max Min Max Min Max Min Max Min Max Unit Output Times – 0.45 – 0.45 – 0.45 – 0.45 – 0.50 ns – –0.45 – –0.45 – –0.45 – –0.50 – ns – 0.45 – 0.45 – 0.45 – 0.45 – 0.50 ns –0.45 – –0.45 – –0.45 – –0.45 – –0.50 – ns 0.40 ns –0.
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CY7C1511KV18, CY7C1526KV18 CY7C1513KV18, CY7C1515KV18 Switching Waveforms Figure 5.
PAGE 27
CY7C1511KV18, CY7C1526KV18 CY7C1513KV18, CY7C1515KV18 Ordering Information The following table lists all possible speed, package, and temperature range options supported for these devices. Note that some options listed may not be available for order entry. To verify the availability of a specific option, visit the Cypress website at www.cypress.com and refer to the product summary page at http://www.cypress.com/products or contact your local sales representative for the status of availability of parts.
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CY7C1511KV18, CY7C1526KV18 CY7C1513KV18, CY7C1515KV18 Table 2. Ordering Information (continued) Speed (MHz) 250 Ordering Code CY7C1511KV18-250BZC Package Diagram Package Type 51-85180 165-Ball Fine Pitch Ball Grid Array (13 x 15 x 1.4 mm) Operating Range Commercial CY7C1526KV18-250BZC CY7C1513KV18-250BZC CY7C1515KV18-250BZC CY7C1511KV18-250BZXC 51-85180 165-Ball Fine Pitch Ball Grid Array (13 x 15 x 1.
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CY7C1511KV18, CY7C1526KV18 CY7C1513KV18, CY7C1515KV18 Table 2. Ordering Information (continued) Speed (MHz) 167 Ordering Code CY7C1511KV18-167BZC Package Diagram Package Type 51-85180 165-Ball Fine Pitch Ball Grid Array (13 x 15 x 1.4 mm) Operating Range Commercial CY7C1526KV18-167BZC CY7C1513KV18-167BZC CY7C1515KV18-167BZC CY7C1511KV18-167BZXC 51-85180 165-Ball Fine Pitch Ball Grid Array (13 x 15 x 1.
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CY7C1511KV18, CY7C1526KV18 CY7C1513KV18, CY7C1515KV18 Package Diagram Figure 6. 165-Ball FBGA (13 x 15 x 1.4 mm), 51-85180 BOTTOM VIEW PIN 1 CORNER TOP VIEW Ø0.05 M C Ø0.25 M C A B PIN 1 CORNER Ø0.50 -0.06 (165X) +0.14 1 2 3 4 5 6 7 8 9 10 11 11 9 8 7 6 5 4 3 2 1 A B B C C 1.00 A D D E F F G G H J 14.00 E 15.00±0.10 15.00±0.10 10 H J K L L 7.00 K M M N N P P R R A A 1.00 5.00 10.00 B B 13.00±0.10 13.00±0.10 1.40 MAX. 0.15 C 0.53±0.05 0.
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CY7C1511KV18, CY7C1526KV18 CY7C1513KV18, CY7C1515KV18 Document History Page Document Title: CY7C1511KV18/CY7C1526KV18/CY7C1513KV18/CY7C1515KV18, 72-Mbit QDR™-II SRAM 4-Word Burst Architecture Document Number: 001-00435 Rev. ECN No. Orig.