AutoStore nvSRAM Specification Sheet

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STK12C68

64 Kbit (8K x 8) AutoStore nvSRAM

Cypress Semiconductor Corporation • 198 Champion Court • San Jose

CA 95134-1709 • 408-943-2600

Document Number: 001-51027 Rev. ** Revised January 30, 2009

Features

■

25 ns, 35 ns, and 45 ns access times

■

Hands off automatic STORE on power down with external 68

µF capacitor

■

STORE to QuantumTrap™ nonvolatile elements is initiated by

software, hardware, or AutoStore™ on power down

■

RECALL to SRAM initiated by software or power up

■

Unlimited Read, Write, and Recall cycles

■

1,000,000 STORE cycles to QuantumTrap

■

100 year data retention to QuantumTrap

■

Single 5V+10% operation

■

Commercial and industrial temperatures

■

228-pin (330mil) SOIC, 28-pin (300mil) PDIP, 28-pin (600mil)

PDIP packages

■

28-pin (300 mil) CDIP and 28-pad (350 mil) LCC packages

■

RoHS compliance

Functional Description

The Cypress STK12C68 is a fast static RAM with a nonvolatile

element in each memory cell. The embedded nonvolatile

elements incorporate QuantumTrap technology producing the

world’s most reliable nonvolatile memory. The SRAM provides

unlimited read and write cycles, while independent nonvolatile

data resides in the highly reliable QuantumTrap cell. Data

transfers from the SRAM to the nonvolatile elements (the

STORE operation) takes place automatically at power down. On

power up, data is restored to the SRAM (the RECALL operation)

from the nonvolatile memory. Both the STORE and RECALL

operations are also available under software control. A hardware

STORE is initiated with the HSB

pin.

STORE/

RECALL

CONTROL

POWER

CONTROL

SOFTWARE

DETECT

STATIC RAM

ARRAY

128 X 512

Quantum Trap

128 X 512

STORE

RECALL

COLUMN I/O

COLUMN DEC

ROW DECODER

INPUT BUFFERS

HSB

CAP

Logic Block Diagram

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Summary of content (20 pages)

PAGE 1
STK12C68 64 Kbit (8K x 8) AutoStore nvSRAM Features Functional Description ■ 25 ns, 35 ns, and 45 ns access times ■ Hands off automatic STORE on power down with external 68 µF capacitor ■ STORE to QuantumTrap™ nonvolatile elements is initiated by software, hardware, or AutoStore™ on power down ■ RECALL to SRAM initiated by software or power up ■ Unlimited Read, Write, and Recall cycles ■ 1,000,000 STORE cycles to QuantumTrap ■ 100 year data retention to QuantumTrap The Cypress STK12C68 is a
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STK12C68 Pin Configurations Figure 1. 28-Pin SOIC/DIP and LLC Pin Definitions Pin Name Alt A0–A12 IO Type Input DQ0-DQ7 Description Address Inputs. Used to select one of the 8,192 bytes of the nvSRAM. Input or Output Bidirectional Data IO Lines. Used as input or output lines depending on operation. WE W Input Write Enable Input, Active LOW. When the chip is enabled and WE is LOW, data on the IO pins is written to the specific address location. CE E Input Chip Enable Input, Active LOW.
PAGE 3
STK12C68 Device Operation The STK12C68 nvSRAM is made up of two functional components paired in the same physical cell. These are an SRAM memory cell and a nonvolatile QuantumTrap cell. The SRAM memory cell operates as a standard fast static RAM. Data in the SRAM is transferred to the nonvolatile cell (the STORE operation) or from the nonvolatile cell to SRAM (the RECALL operation). This unique architecture enables the storage and recall of all cells in parallel.
PAGE 4
STK12C68 9FF :( N 2KP 9&$3 N 2KP 5 ) %\SDVV Figure 3. AutoStore Inhibit Mode +6% During any STORE operation, regardless of how it is initiated, the STK12C68 continues to drive the HSB pin LOW, releasing it only when the STORE is complete. After completing the STORE operation, the STK12C68 remains disabled until the HSB pin returns HIGH. If HSB is not used, it is left unconnected.
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STK12C68 3. Read address 0x0AAA, Valid READ 4. Read address 0x1FFF, Valid READ 5. Read address 0x10F0, Valid READ 6. Read address 0x0F0E, Initiate RECALL cycle ■ The VCC level ■ IO loading Figure 4. Current Versus Cycle Time (Read) Internally, RECALL is a two step procedure. First, the SRAM data is cleared; then, the nonvolatile information is transferred into the SRAM cells. After the tRECALL cycle time, the SRAM is again ready for Read and Write operations.
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STK12C68 Best Practices manufacturing test to ensure these system routines work consistently. nvSRAM products have been used effectively for over 15 years. While ease-of-use is one of the product’s main system values, experience gained working with hundreds of applications has resulted in the following suggestions as best practices: ■ The nonvolatile cells in an nvSRAM are programmed on the test floor during final test and quality assurance.
PAGE 7
STK12C68 Maximum Ratings Voltage on DQ0-7 or HSB .......................–0.5V to Vcc + 0.5V Exceeding maximum ratings may shorten the useful life of the device. These user guidelines are not tested. Storage Temperature ................................. –65°C to +150°C Power Dissipation.......................................................... 1.0W DC output Current (1 output at a time, 1s duration) .... 15 mA Operating Range Temperature under Bias .............................
PAGE 8
STK12C68 Data Retention and Endurance Parameter Description DATAR Data Retention NVC Nonvolatile STORE Operations Min Unit 100 Years 1,000 K Capacitance In the following table, the capacitance parameters are listed.[6] Parameter Description CIN Input Capacitance COUT Output Capacitance Test Conditions TA = 25°C, f = 1 MHz, VCC = 0 to 3.0 V Max Unit 8 pF 7 pF Thermal Resistance In the following table, the thermal resistance parameters are listed.
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STK12C68 AC Switching Characteristics SRAM Read Cycle Parameter Cypress Alt Parameter tACE tELQV tAVAV, tELEH tRC [7] tAVQV tAA [8] tGLQV tDOE tAXQX tOHA [8] tELQX tLZCE [9] tEHQZ tHZCE [9] [9] tGLQX tLZOE tGHQZ tHZOE [9] tELICCH tPU [6] [6] tEHICCL tPD 25 ns Description Min Chip Enable Access Time Read Cycle Time Address Access Time Output Enable to Data Valid Output Hold After Address Change Chip Enable to Output Active Chip Disable to Output Inactive Output Enable to Output Active Output Disable to Ou
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STK12C68 SRAM Write Cycle Parameter Cypress Parameter 25 ns Description Alt tWC tPWE tSCE tSD tHD tAW tSA tHA tHZWE [9,10] tLZWE [9] tAVAV tWLWH, tWLEH tELWH, tELEH tDVWH, tDVEH tWHDX, tEHDX tAVWH, tAVEH tAVWL, tAVEL tWHAX, tEHAX tWLQZ tWHQX Min Write Cycle Time Write Pulse Width Chip Enable To End of Write Data Setup to End of Write Data Hold After End of Write Address Setup to End of Write Address Setup to Start of Write Address Hold After End of Write Write Enable to Output Disable Output Active Af
PAGE 11
STK12C68 AutoStore or Power Up RECALL Parameter Alt tHRECALL [13] tSTORE [14, 15, 16] tDELAY [9, 15] VSWITCH VRESET tVCCRISE tVSBL[11] tRESTORE tHLHZ tHLQZ , tBLQZ Description Power up RECALL Duration STORE Cycle Duration Time Allowed to Complete SRAM Cycle Low Voltage Trigger Level Low Voltage Reset Level VCC Rise Time Low Voltage Trigger (VSWITCH) to HSB Low STK12C68 Min Max 550 10 1 4.0 4.5 3.9 150 300 Unit μs ms μs V V μs ns Switching Waveform Figure 11. AutoStore/Power Up RECALL WE Notes 13.
PAGE 12
STK12C68 Software Controlled STORE/RECALL Cycle The software controlled STORE/RECALL cycle follows. [18] Parameter Alt Description 25 ns Min 35 ns Max Min Max 45 ns Min Max Unit tRC[14] tAVAV STORE/RECALL Initiation Cycle Time 25 35 45 ns [17] tAVEL Address Setup Time 0 0 0 ns tCW[17] tHACE[17] tELEH Clock Pulse Width 20 25 30 ns tELAX Address Hold Time 20 20 20 ns tSA RECALL Duration tRECALL 20 20 20 μs Switching Waveform Figure 12.
PAGE 13
STK12C68 Hardware STORE Cycle Parameter tSTORE [9, 14] tDHSB tPHSB [14, 19] Alt tHLHZ Description STK12C68 Min STORE Cycle Duration tRECOVER, tHHQX Hardware STORE High to Inhibit Off tHLHX tHLBL Hardware STORE Pulse Width Hardware STORE Low to STORE Busy Max Unit 10 ms 700 ns 15 ns 300 ns Switching Waveform Figure 13. Hardware STORE Cycle Note 19. tDHSB is only applicable after tSTORE is complete. Document Number: 001-51027 Rev.
PAGE 14
STK12C68 Part Numbering nomenclature STK12C68 - S F 45 I TR Packaging Option: TR = Tape and Reel Blank = Tube Temperature Range: C - Commercial (0 to 70°C) I - Industrial (-40 to 85°C) Lead Finish Speed: 25 - 25 ns 35 - 35 ns 45 - 45 ns F = 100% Sn (Matte Tin) Package: S = Plastic 28-pin 330 mil SOIC P = Plastic 28-pin 300 mil DIP W = Plastic 28-pin 600 mil DIP C = Ceramic 28-pin 300 mil DIP L = Ceramic 28-pin LLC Ordering Information Speed (ns) 25 35 Ordering Code Package Diagram Package Type STK
PAGE 15
STK12C68 Ordering Information (continued) Speed (ns) 45 Ordering Code Package Diagram Package Type STK12C68-SF45TR 001-85058 28-pin SOIC (330 mil) STK12C68-SF45 001-85058 28-pin SOIC (330 mil) STK12C68-PF45 001-85014 28-pin PDIP (300 mil) STK12C68-WF45 001-85017 28-pin PDIP (600 mil) STK12C68-C45 001-51695 28-pin CDIP (300 mil) STK12C68-L45 001-51696 28-pin LCC (350 mil) STK12C68-SF45ITR 001-85058 28-pin SOIC (330 mil) STK12C68-SF45I 001-85058 28-pin SOIC (330 mil) STK12C68-PF45I
PAGE 16
STK12C68 Package Diagrams Figure 14. 28-Pin (330 Mil) SOIC (51-85058) 51-85058 *A Figure 15. 28-Pin (300 Mil) PDIP (51-85014) 51-85014 *D Document Number: 001-51027 Rev.
PAGE 17
STK12C68 Package Diagrams (continued) Figure 16. 28-Pin (600 Mil) PDIP (51-85017) 51-85017 *B Document Number: 001-51027 Rev.
PAGE 18
STK12C68 Package Diagrams (continued) Figure 17. 28-Pin (300 Mil) Side Braze DIL (001-51695) 001-51695 ** Document Number: 001-51027 Rev.
PAGE 19
STK12C68 Package Diagrams (continued) Figure 18. 28-Pad (350 Mil) LCC (001-51696) 1. ALL DIMENSION ARE IN INCHES AND MILLIMETERS [MIN/MAX] 2. JEDEC 95 OUTLINE# MO-041 3. PACKAGE WEIGHT : TBD 001-51696 ** Document Number: 001-51027 Rev.
PAGE 20
STK12C68 Document History Page Document Title: STK12C68 64 Kbit (8K x 8) AutoStore nvSRAM Document Number: 001-51027 Rev. ECN No. Orig. of Change Submission Date ** 2606744 GVCH 01/30/2009 Description of Change New data sheet Sales, Solutions, and Legal Information Worldwide Sales and Design Support Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office closest to you, visit us at cypress.com/sales.