CYV15G0404RB
Document #: 38-02102 Rev. *C Page 5 of 27
WREN
ADDR[3:0]
DATA[7:0]
Device Configuration and Control Block Diagram
= Internal Signal
RXRATE[A..D]
RXBIST[A..D]
SDASEL[A..D][1:0]
RXPLLPD[A..D]
ROE[2..1][A..D]
GLEN[11..0]
FGLEN[2..0]
Device Configuration
and Control Interface
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