SoftStore nvSRAM Specification Sheet

ManualsBrandsCypress ManualsComputer HardwareSTK11C68-5

STK11C68-5 (SMD5962-92324)

64 Kbit (8K x 8) SoftStore nvSRAM

Cypress Semiconductor Corporation • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600

Document Number: 001-51001 Rev. *A Revised April 07, 2009

Features

■ 35 ns, 45 ns, and 55 ns access times

■ Pin compatible with industry standard SRAMs

■ Software initiated nonvolatile STORE

■ Unlimited Read and Write endurance

■ Automatic RECALL to SRAM on power up

■ Unlimited RECALL cycles

■ 1,000,000 STORE cycles

■ 100 year data retention

■ Single 5V ± 10% operation

■ Military temperature

■ 28-pin (300 mil) CDIP and 28-pad LCC packages

Functional Description

The Cypress STK11C68-5 is a 64 Kb fast static RAM with a

nonvolatile element in each memory cell. The embedded

nonvolatile elements incorporate QuantumTrap technology to

produce the world’s most reliable nonvolatile memory. The

SRAM provides unlimited read and write cycles, while

independent nonvolatile data resides in the highly reliable

QuantumTrap cell. Data transfers under software control from

SRAM to the nonvolatile elements (the STORE operation). On

power up, data is automatically restored to the SRAM (the

RECALL operation) from the nonvolatile memory. RECALL

operations are also available under software control.

STORE/

RECALL

CONTROL

POWER

CONTROL

SOFTWARE

DETECT

STATIC RAM

ARRAY

128 X 512

Quantum Trap

128 X 512

STORE

RECALL

COLUMN I/O

COLUMN DEC

ROW DECODER

INPUT BUFFERS

HSB

CAP

- A

Logic Block Diagram

[+] Feedback

Summary of content (15 pages)

PAGE 1
STK11C68-5 (SMD5962-92324) 64 Kbit (8K x 8) SoftStore nvSRAM Features Functional Description ■ 35 ns, 45 ns, and 55 ns access times ■ Pin compatible with industry standard SRAMs ■ Software initiated nonvolatile STORE ■ Unlimited Read and Write endurance ■ Automatic RECALL to SRAM on power up ■ Unlimited RECALL cycles ■ 1,000,000 STORE cycles The Cypress STK11C68-5 is a 64 Kb fast static RAM with a nonvolatile element in each memory cell.
PAGE 2
STK11C68-5 (SMD5962-92324) Pinouts Figure 1. Pin Diagram - 28-Pin DIP 1& 9&& $ $ :( 1& $ $ $ $ $ $ $ $ $ 2( $ $ &( '4 '4 '4 '4 '4 '4 '4 966 '4 723 Figure 2. Pin Diagram - 28-Pin LLC Pin Definitions Pin Name Alt A0–A12 I/O Type Input DQ0-DQ7 Description Address Inputs. Used to select one of the 8,192 bytes of the nvSRAM.
PAGE 3
STK11C68-5 (SMD5962-92324) Device Operation The STK11C68-5 is a versatile memory chip that provides several modes of operation. The STK11C68-5 can operate as a standard 8K x 8 SRAM. It has an 8K x 8 Nonvolatile Elements shadow to which the SRAM information can be copied or from which the SRAM can be updated in nonvolatile mode. The software sequence is clocked with CE controlled Reads. When the sixth address in the sequence is entered, the STORE cycle commences and the chip is disabled.
PAGE 4
STK11C68-5 (SMD5962-92324) Low Average Active Power Figure 4. Current Versus Cycle Time (Write) CMOS technology provides the STK11C68-5 the benefit of drawing significantly less current when it is cycled at times longer than 50 ns. Figure 3 and Figure 4 shows the relationship between ICC and Read or Write cycle time. Worst case current consumption is shown for both CMOS and TTL input levels (commercial temperature range, VCC = 5.5V, 100% duty cycle on chip enable).
PAGE 5
STK11C68-5 (SMD5962-92324) Maximum Ratings Voltage on DQ0-7 ...................................–0.5V to Vcc + 0.5V Exceeding maximum ratings may shorten the useful life of the device. These user guidelines are not tested. Storage Temperature ................................. –65°C to +150°C Power Dissipation ......................................................... 1.0W DC Output Current (1 output at a time, 1s duration).... 15 mA Operating Range Temperature under bias..............................
PAGE 6
STK11C68-5 (SMD5962-92324) Thermal Resistance In this table, the thermal resistance parameters are listed.[3] Parameter ΘJA ΘJC Description Thermal Resistance (Junction to Ambient) Thermal Resistance (Junction to Case) Test Conditions 28-CDIP 28-LCC Unit Test conditions follow standard test methods and procedures for measuring thermal impedance, per EIA / JESD51. TBD TBD °C/W TBD TBD °C/W Figure 5. AC Test Loads R1 480Ω 5.0V Output 30 pF R2 255Ω AC Test Conditions Input Pulse Levels .......
PAGE 7
STK11C68-5 (SMD5962-92324) AC Switching Characteristics SRAM Read Cycle Parameter Cypress Alt Parameter tELQV tACE [4] tAVAV, tRC tELEH tAVQV tAA [5] 35 ns Description Min Chip Enable Access Time Read Cycle Time 45 ns Max Min 35 35 55 ns Max Min 45 45 Max Unit 55 ns ns 55 Address Access Time 35 45 55 ns tGLQV tAXQX Output Enable to Data Valid Output Hold After Address Change 15 20 35 5 5 5 ns ns tLZCE [6] tELQX Chip Enable to Output Active 5 5 5 ns tHZCE [6] tEHQZ C
PAGE 8
STK11C68-5 (SMD5962-92324) SRAM Write Cycle Parameter Cypress Alt Parameter tAVAV tWC tWLWH, tWLEH tPWE tELWH, tELEH tSCE tSD tDVWH, tDVEH tWHDX, tEHDX tHD tAVWH, tAVEH tAW tSA tAVWL, tAVEL tWHAX, tEHAX tHA [6,7] tWLQZ tHZWE Write Cycle Time Write Pulse Width Chip Enable To End of Write Data Setup to End of Write Data Hold After End of Write Address Setup to End of Write Address Setup to Start of Write Address Hold After End of Write Write Enable to Output Disable 35 25 25 12 0 25 0 0 tLZWE [6] Output A
PAGE 9
STK11C68-5 (SMD5962-92324) AutoStore INHIBIT or Power Up RECALL Parameter Alt STK11C68-5 Description Min Max Unit tHRECALL [9] tRESTORE Power up RECALL Duration 550 μs tSTORE STORE Cycle Duration 10 ms 4.5 V 3.6 V tHLHZ VSWITCH Low Voltage Trigger Level VRESET Low Voltage Reset Level 4.0 Figure 10.
PAGE 10
STK11C68-5 (SMD5962-92324) Software Controlled STORE/RECALL Cycle The software controlled STORE/RECALL cycle follows. [10, 11] Parameter Alt Description 35 ns Min 45 ns Max Min 55 ns Max Min Max Unit tRC tAVAV STORE/RECALL Initiation Cycle Time 35 45 55 ns tSA[10] tCW[10] tHACE[10] tRECALL[10] tAVEL Address Setup Time 0 0 0 ns tELEH Clock Pulse Width 25 30 35 ns tELAX Address Hold Time 20 20 20 ns RECALL Duration 20 20 20 μs Switching Waveform Figure 11.
PAGE 11
STK11C68-5 (SMD5962-92324) Part Numbering Nomenclature STK11C68 - 5 C 45 M Temperature Range: M - Military (-55 to 125°C) Speed: 35 - 35 ns 45 - 45 ns 55 - 55 ns Package: C = Ceramic 28-pin 300 mil DIP (gold lead finish) K = Ceramic 28-pin 300 mil DIP (Solder dip finish) L = Ceramic 28-pin LLC Retention / Endurance 5 = Military (10 years or 105 cycles) SMD5962-92324 04 MX X Lead Finish A = Solder DIP lead finish C = Gold lead DIP finish X = Lead finish “A” or “C” is acceptable Case Outline X = Ceramic
PAGE 12
STK11C68-5 (SMD5962-92324) Ordering Information Speed (ns) 35 45 55 Ordering Code Package Diagram Package Type STK11C68-5C35M 001-51695 28-Pin CDIP (300 mil) STK11C68-5K35M 001-51695 28-Pin CDIP (300 mil) STK11C68-5L35M 001-51696 28-Pin LCC (350 mil) STK11C68-5C45M 001-51695 28-Pin CDIP (300 mil) STK11C68-5K45M 001-51695 28-Pin CDIP (300 mil) STK11C68-5L45M 001-51696 28-Pin LCC (350 mil) STK11C68-5C55M 001-51695 28-Pin CDIP (300 mil) STK11C68-5K55M 001-51695 28-Pin CDIP (300 mil
PAGE 13
STK11C68-5 (SMD5962-92324) Package Diagrams Figure 12. 28-Pin (300-Mil) Side Braze DIL (001-51695) 001-51695 ** Document Number: 001-51001 Rev.
PAGE 14
STK11C68-5 (SMD5962-92324) Package Diagrams (continued) Figure 13. 28-Pad (350-Mil) LCC (001-51696) 1. ALL DIMENSION ARE IN INCHES AND MILLIMETERS [MIN/MAX] 2. JEDEC 95 OUTLINE# MO-041 3. PACKAGE WEIGHT : TBD 001-51696 ** Document Number: 001-51001 Rev.
PAGE 15
STK11C68-5 (SMD5962-92324) Document History Page Document Title: STK11C68-5 (SMD5962-92324) 64 Kbit (8K x 8) SoftStore nvSRAM Document Number: 001-51001 Rev. ECN No. Orig.