SoftStore nvSRAM Specification Sheet

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STK11C68

64 Kbit (8K x 8) SoftStore nvSRAM

Cypress Semiconductor Corporation • 198 Champion Court • San Jose

CA 95134-1709 • 408-943-2600

Document Number: 001-50638 Rev. ** Revised January 30, 2009

Features

■

25 ns, 35 ns, and 45 ns access times

■

Pin compatible with industry standard SRAMs

■

Software initiated nonvolatile STORE

■

Unlimited Read and Write endurance

■

Automatic RECALL to SRAM on power up

■

Unlimited RECALL cycles

■

1,000,000 STORE cycles

■

100 year data retention

■

Single 5V+10% operation

■

Commercial and industrial temperature

■

28-pin (330 mil) SOIC package

■

28-pin (300 mil) CDIP and 28-pad (350 mil) LCC packages

■

RoHS compliance

Functional Description

The Cypress STK11C68 is a 64Kb fast static RAM with a nonvol-

atile element in each memory cell. The embedded nonvolatile

elements incorporate QuantumTrap technology producing the

world’s most reliable nonvolatile memory. The SRAM provides

unlimited read and write cycles, while independent nonvolatile

data resides in the highly reliable QuantumTrap cell. Data

transfers under software control from SRAM to the nonvolatile

elements (the STORE operation). On power up, data is automat-

ically restored to the SRAM (the RECALL operation) from the

nonvolatile memory. RECALL operations are also available

under software control.

STORE/

RECALL

CONTROL

POWER

CONTROL

SOFTWARE

DETECT

STATIC RAM

ARRAY

128 X 512

Quantum Trap

128 X 512

STORE

RECALL

COLUMN I/O

COLUMN DEC

ROW DECODER

INPUT BUFFERS

HSB

CAP

Logic Block Diagram

[+] Feedback

Summary of content (16 pages)

PAGE 1
STK11C68 64 Kbit (8K x 8) SoftStore nvSRAM Features Functional Description ■ 25 ns, 35 ns, and 45 ns access times ■ Pin compatible with industry standard SRAMs ■ Software initiated nonvolatile STORE ■ Unlimited Read and Write endurance ■ Automatic RECALL to SRAM on power up ■ Unlimited RECALL cycles ■ 1,000,000 STORE cycles The Cypress STK11C68 is a 64Kb fast static RAM with a nonvolatile element in each memory cell.
PAGE 2
STK11C68 Pin Configurations Figure 1. Pin Diagram - 28-Pin SOIC/DIP and 28-Pin LLC 1& 9&& $ $ :( 1& $ $ $ $ $ $ $ $ $ $ 723 2( $ &( '4 '4 '4 '4 '4 '4 '4 966 '4 Pin Definitions Pin Name Alt IO Type A0–A12 Input DQ0-DQ7 Input or Output Description Address Inputs. Used to select one of the 8,192 bytes of the nvSRAM. Bidirectional Data IO Lines.
PAGE 3
STK11C68 Device Operation The STK11C68 is a versatile memory chip that provides several modes of operation. The STK16C88 can operate as a standard 8K x 8 SRAM. A 8K x 8 array of nonvolatile storage elements shadow the SRAM. SRAM data can be copied nonvolatile memory or nonvolatile data can be recalled to the SRAM. SRAM Read The STK11C68 performs a Read cycle whenever CE and OE are LOW while WE is HIGH. The address specified on pins A0–12 determines the 8,192 data bytes accessed.
PAGE 4
STK11C68 average current drawn by the STK11C68 depends on the following items: ■ The duty cycle of chip enable ■ The overall cycle rate for accesses ■ The ratio of Reads to Writes ■ CMOS versus TTL input levels ■ The operating temperature ■ The VCC level Best Practices nvSRAM products have been used effectively for over 15 years.
PAGE 5
STK11C68 Maximum Ratings Power Dissipation ......................................................... 1.0W Exceeding maximum ratings may shorten the useful life of the device. These user guidelines are not tested. DC Output Current (1 output at a time, 1s duration).... 15 mA Operating Range Storage Temperature ................................. –65°C to +150°C Temperature under bias.............................. –55°C to +125°C Range Supply Voltage on VCC Relative to GND ..........–0.5V to 7.
PAGE 6
STK11C68 Capacitance In the following table, the capacitance parameters are listed.[3] Parameter Description CIN Input Capacitance COUT Output Capacitance Test Conditions TA = 25°C, f = 1 MHz, VCC = 0 to 3.0V Max Unit 8 pF 7 pF Thermal Resistance In the following table, the thermal resistance parameters are listed.
PAGE 7
STK11C68 AC Switching Characteristics SRAM Read Cycle Parameter Cypress Alt Parameter tELQV tACE tAVAV, tELEH tRC [4] tAVQV tAA [5] tGLQV tDOE tAXQX tOHA [5] tELQX tLZCE [6] tEHQZ tHZCE [6] [6] tGLQX tLZOE tGHQZ tHZOE [6] tELICCH tPU [3] [3] tEHICCL tPD 25 ns Description Min Chip Enable Access Time Read Cycle Time Address Access Time Output Enable to Data Valid Output Hold After Address Change Chip Enable to Output Active Chip Disable to Output Inactive Output Enable to Output Active Output Disable to Ou
PAGE 8
STK11C68 SRAM Write Cycle Parameter Cypress Parameter 25 ns Description Alt tAVAV tWLWH, tWLEH tELWH, tELEH tDVWH, tDVEH tWHDX, tEHDX tAVWH, tAVEH tAVWL, tAVEL tWHAX, tEHAX tWLQZ tWHQX tWC tPWE tSCE tSD tHD tAW tSA tHA tHZWE [6,7] tLZWE [6] Min Write Cycle Time Write Pulse Width Chip Enable To End of Write Data Setup to End of Write Data Hold After End of Write Address Setup to End of Write Address Setup to Start of Write Address Hold After End of Write Write Enable to Output Disable Output Active Afte
PAGE 9
STK11C68 AutoStore INHIBIT or Power Up RECALL Parameter tHRECALL [9] tSTORE VSWITCH VRESET Alt tRESTORE tHLHZ Description Power up RECALL Duration STORE Cycle Duration Low Voltage Trigger Level Low Voltage Reset Level STK11C68 Max 550 10 4.0 4.5 3.6 Min Unit μs ms V V Switching Waveform Figure 9.
PAGE 10
STK11C68 Software Controlled STORE/RECALL Cycle The software controlled STORE/RECALL cycle follows. [10, 11] Parameter tRC tSA [10] tCW[10] tHACE[10] tRECALL[10] Alt Description 25 ns Min 35 ns Max Min 45 ns Max Min Max Unit tAVAV STORE/RECALL Initiation Cycle Time 25 35 45 ns tAVEL Address Setup Time 0 0 0 ns tELEH Clock Pulse Width 20 25 30 ns tELAX Address Hold Time 20 20 20 ns RECALL Duration 20 20 20 μs Switching Waveform Figure 10.
PAGE 11
STK11C68 Part Numbering Nomenclature STK11C68 - S F 45 I TR Packaging Option: TR = Tape and Reel Blank = Tube Temperature Range: Blank - Commercial (0 to 70°C) I - Industrial (-40 to 85°C) Lead Finish Speed: 25 - 25 ns 35 - 35 ns 45 - 45 ns F = 100% Sn (Matte Tin) Package: S = Plastic 28-pin 330 mil SOIC C = Ceramic 28-pin 300 mil DIP L = Ceramic 28-pin 350 mil LLC Ordering Information Speed (ns) 25 35 Ordering Code Package Diagram Package Type STK11C68-SF25TR 001-85058 28-Pin SOIC (330 mil) S
PAGE 12
STK11C68 Ordering Information (continued) Speed (ns) 45 Ordering Code Package Diagram Package Type STK11C68-SF45TR 001-85058 28-Pin SOIC (330 mil) STK11C68-SF45 001-85058 28-Pin SOIC (330 mil) STK11C68-C45 001-51695 28-Pin CDIP (300 mil) STK11C68-L45 001-51696 28-Pin LCC (350 mil) STK11C68-SF45ITR 001-85058 28-Pin SOIC (330 mil) STK11C68-SF45I 001-85058 28-Pin SOIC (330 mil) STK11C68-C45I 001-51695 28-Pin CDIP (300 mil) STK11C68-L45I 001-51696 28-Pin LCC (350 mil) Operating Range
PAGE 13
STK11C68 Package Diagrams Figure 11. 28-Pin (330 Mil) SOIC (51-85058) 51-85058 *A Document Number: 001-50638 Rev.
PAGE 14
STK11C68 Package Diagrams (continued) Figure 12. 28-Pin (300 Mil) Side Braze DIL (001-51695) 001-51695 ** Document Number: 001-50638 Rev.
PAGE 15
STK11C68 Package Diagrams (continued) Figure 13. 28-Pad (350 Mil) LCC (001-51696) 1. ALL DIMENSION ARE IN INCHES AND MILLIMETERS [MIN/MAX] 2. JEDEC 95 OUTLINE# MO-041 001-51696 ** 3. PACKAGE WEIGHT : TBD Document Number: 001-50638 Rev.
PAGE 16
STK11C68 Document History Page Document Title: STK11C68 64 Kbit (8K x 8) SoftStore nvSRAM Document Number: 001-50638 Rev. ECN No. Orig. of Change Submission Date ** 2625084 GVCH/PYRS 01/30/09 Description of Change New data sheet Sales, Solutions, and Legal Information Worldwide Sales and Design Support Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office closest to you, visit us at cypress.com/sales.