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CY24713

Set-top Box Clock Generator with VCXO

Cypress Semiconductor Corporation • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600

Document #: 38-07396 Rev. *A Revised May 22, 2008

Features

■ Integrated phase-locked loop (PLL)

■ Low-jitter, high-accuracy outputs

■ VCXO with analog adjust

■ 3.3V Operation

■ 8-pin SOIC

Benefits

■ High-performance PLL tailored for Set Top Box applications

■ Meets critical timing requirements in complex system designs

■ Large ±150-ppm range, better linearity

■ Meet industry standard voltage platforms

■ Industry standard packaging saves on board space

Pin Configuration

Figure 1. CY24713, 8-Pin SOIC

Part Number Outputs Input Frequency Range Output Frequencies

CY24713 3 27-MHz pullable crystal input

per Cypress specification

4.9152 MHz, 13.5 MHz, 27 MHz

Logic Block Diagram

Table 1. Pin Definition

Name Number Description

XIN 1 Reference Crystal Input

VDD 2 3.3V Voltage Supply

VCXO 3 Input Analog Control for VCXO

VSS 4 Ground

CLK_B 5 13.5-MHz Clock Output

CLK_A 6 4.9152-MHz Clock Output

CLK_C 7 27-MHz Clock Output

XOUT

[1]

8 Reference Crystal Output

Note

1. Float X

OUT

if X

is externally driven.

[+] Feedback

Summary of content (5 pages)

PAGE 1
CY24713 Set-top Box Clock Generator with VCXO Features Benefits ■ Integrated phase-locked loop (PLL) ■ High-performance PLL tailored for Set Top Box applications ■ Low-jitter, high-accuracy outputs ■ Meets critical timing requirements in complex system designs ■ VCXO with analog adjust ■ Large ±150-ppm range, better linearity ■ 3.
PAGE 2
CY24713 Absolute Maximum Conditions Parameter VDD Description Min Max Unit –0.5 7.0 V –65 125 °C – 125 °C Digital Inputs VSS – 0.3 VDD + 0.3 V Digital Outputs referred to VDD VSS – 0.3 VDD + 0.3 V – 2000 V –0.5 7.0 V Supply Voltage [2] TS Storage Temperature TJ Junction Temperature Electrostatic Discharge Analog Input Pullable Crystal Specifications Parameter Description Condition Min Typ.
PAGE 3
CY24713 AC Electrical Characteristics (VDD = 3.3V) Parameter[3] Description Conditions Min Typ. Max Unit DC Output Duty Cycle Duty Cycle is defined in Figure 3 50% of VDD 45 50 55 % ER0 Rising Edge Rate Output Clock Edge Rate, Measured from 20% to 80% of VDD, CLOAD = 15 pF Figure 4. 0.8 1.4 – V/ns EF1 Falling Edge Rate Output Clock Edge Rate, Measured from 80% to 20% of VDD, CLOAD = 15 pF Figure 4. 0.8 1.
PAGE 4
CY24713 Ordering Information Ordering Code Package Type Operating Range Operating Voltage CY24713SC[4] 8-pin SOIC Commercial 3.3V [4] 8-pin SOIC Commercial 3.3V CY24713SXC[4] 8-pin SOIC Commercial 3.3V CY24713SXCT[4] 8-pin SOIC-Tape and Reel Commercial 3.3V CY24713KSXC 8-pin SOIC Commercial 3.3V CY24713KSXCT 8-pin SOIC-Tape and Reel Commercial 3.3V CY24713SCT Pb-free Package Diagram Figure 5. 8-Lead (150-Mil) SOIC S8 PIN 1 ID 4 1 1. DIMENSIONS IN INCHES[MM] MIN. MAX. 2.
PAGE 5
CY24713 Document History Page Document Title: CY24713 Set-top Box Clock Generator with VCXO Document Number: 38-07396 REV. ECN No. Orig. of Change Submission Date ** 333175 RGL See ECN New Data Sheet *A 2440886 AESA See ECN Updated template. Added Note “Not recommended for new designs.” Added part number CY24713KSXC, and CY24713KSXCT in ordering information table. Replaced Lead-Free with Pb-Free.