Service manual

CP-850FX Service Manual

Europe R&D

pass filtered with the according gain and time constant. The result is used to attenuate the RGB

outputs by adjusting the white drive multipliers for the internal (digital) RGB signals, and the

analog contrast multipliers for the analog RGB inputs, respectively. The lower limit of the

attenuator is programmable, thus a minimum contrast can always be set. If the minimum contrast

is reached, the brightness will be decreased to a programmable minimum as well.

5.4.2.13 Synchronization and Deflection

The deflection processing generates the signals for the horizontal and vertical drive. This block

contains two numeric phase-locked loops and a security unit:

– PLL2 generates the horizontal and vertical timing, e.g. blanking, clamping and sync signals.

Phase and frequency are synchronised by the incoming sync signals.

– PLL3 adjusts the phase of the horizontal drive pulse and compensates for the delay of the

horizontal output stage.

– The security unit observes the H-Drive output signal.

With an external 5 MHz reference clock this unit

controls the H-drive “off time” and period. In case of

an incorrect H-drive signal the security unit generates

a free running h-drive signal divided down from

beam current

5.4.2.14 EHT Compensation

The vertical deflection waveform is scaled according the average beam current. This is used to

compensate the effects of electric high tension changes due to beam current variations. EHT

compensation for East/West deflection is done with an offset corresponding to the average beam

current.

5.5 MICRONTROLLER

5.5.1 MICROCONTROLLER FEATURES

 8-bit 8051 instruction set compatible CPU

 33.33-MHz internal clock (max.)

 0.360 μs (min.) instruction cycle

 Two 16-bit timers : schedule software tasks , and user clock

 Watchdog timer

 Capture compare timer for infrared remote control decoding

 Pulse width modulation unit (2 channels 14 bit, 6 channels 8 bit) : used to control AGC

Take Over Point .

 ADC (4 channels, 8 bit) : AFT, AGC, Local keys, OCP.

 UART

5.5.2 ACQUISITION FEATURES

 Multistandard Digital Data Slicer

 Parallel Multi-norm Slicing (TTX, VPS, WSS)

 Four Different Framing Codes Available

 Data Caption only Limited by available Memory

 Programmable VBI-buffer

 Full Channel Data Slicing Supported

 Fully Digital Signal Processing

 Noise Measurement and Controlled Noise Compensation

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