User's Manual

Doc. No.
Rev.
Date
1.00
2011-12-08
Damm Cellular Systems A/S, Denmark
TETRAFLEX
®
V7.5 MANUAL - TR412 Transceiver Description
TetraFlex® 7.5 Manual 4-20
Running with a DSB signal with 60W pep the forward leg IM3 of about 30dBc. The linearity is
improved with the loop gain of about 40dB to reach the Adjacent Channel Power specification
for TETRA of 60dB with good margin.
Hardware and software support is provided for open-loop operation with different modulation
types to allow easy adjustment and test of the transmitter.
A dual RMS power detector is provided on the main board to permit the read-out of forward
and reflected power from the controller as well as for alarm monitoring.
At the TX output the RF Test Loop switch unit is provided with a BNC connector on the front
plate. This allows the controller to activate a test output from the TX with an accurately
calibrated level of –40dBr and –50dBr relative to the TX output. In off state the maximum
level of –80dBr.
4.4.4 Reference oscillators
The TR412 is normally running fully frequency and time synchronized with the BSC. The
synchronization is done with the 2.048MHz, the 8kHz and the 1sec. hardware signals and the
1 sec. HDLC message, all coming from the BSC.
The TR412 contains a 12.8MHz VCXO, which is phase locked to the 2.048MHz input signal.
This acts as reference for the RX and TX frequencies.
The TR412 also contains a 36.864MHz VCXO, which is phase locked to the 8kHz input
signal. This acts as clock reference for the controller, the DSP and for the ADC and DAC and
thereby the TETRA symbol-generation.
The TX and RX TETRA framing is normally time synchronized to the 1-second hardware
input signal together with the information provided in the HDLC message. This ensures that
all TETRA counters are running synchronized on the whole BS. If GPS synchronization is
present on the BSC, it will also run synchronized with surrounding Base Stations.
4.4.5 DSP
The TR412 is provided with a single high performance DSP handling modulation and de-
modulation task directly in software. This gives a high degree of freedom to adapt to any
changes necessary. When running in TETRA mode the DSP also handles the LMAC and
UMAC protocol parts.
The DSP is connected directly via its serial interface to the PCM highway on the back-plane.
Four timeslots are reserved for each TR position. All circuit-mode communication is going this
way to the PCM switch in the BSC.
The MC is connected to the DSP through its host port and controls its functionality, including
software installation and booting. All packed-type communication also passes the host port of
the DSP and goes to the BSC via the MC and the HDLC bus.